Atomic Data Access via Cache Coherency Control
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Solution Overview
Problem
Existing data processing systems face performance penalties and increased complexity in providing atomic behavior for data access operations, particularly when ensuring multiple data items are kept in synchronism and maintaining security, as seen in the use of database locks which can significantly slow processing.
Innovation Solution
The system employs a data processing system with a processor core, cache memory, and interconnect circuitry that manages coherence using MESI protocol and access control circuitry to ensure atomic access to capability and TAG values, allowing multiple data accesses to be performed as an atomic set with low latency by managing coherency statuses and using snoop requests to maintain data integrity and security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If database locks are used to ensure atomic updates to multiple data instances, then data consistency and security are improved, but processing speed and system performance deteriorate significantly
Solution Approach 1:
The system divides the atomic operation requirement into two separate access patterns: speculative accesses that can proceed in parallel without locking, and final commit operations that use lightweight version checks. This segmentation allows most operations to proceed without the performance penalty of traditional database locks, while still ensuring atomicity when needed.
Solution Approach 2:
The patent introduces an intermediary mechanism using memory barriers and version tags as mediators between multiple threads accessing shared data. Instead of using heavy-weight database locks, the system uses these intermediaries to coordinate access and ensure atomicity, significantly reducing the performance overhead while maintaining data consistency.
2Reliability
If traditional locking mechanisms are implemented to ensure atomic behavior, then data synchronism is improved, but system complexity increases
Solution Approach 1:
The patent extracts the complexity of lock management from the application layer and replaces it with hardware-supported memory barriers and automatic version tracking. This takes out the burden of implementing complex locking protocols from software and shifts it to simpler, more efficient hardware mechanisms that are transparent to the programmer.
Solution Approach 2:
The system implements self-service atomic operations where the hardware automatically manages the coordination between threads through memory barriers and version tags. Each thread independently performs speculative accesses and the hardware automatically ensures atomicity without requiring threads to manually acquire or release locks, significantly simplifying the system architecture.
3Productivity
If speculative accesses are allowed in data cache, then processing throughput is improved, but data integrity and atomicity may be compromised
Solution Approach 1:
The patent applies preliminary speculative accesses that proceed without waiting for locks or synchronization. These preliminary actions execute in parallel to improve throughput, and only the final commit operations require coordination. This preliminary execution approach allows the system to maximize throughput while maintaining data integrity through controlled commit points.
Solution Approach 2:
The system uses feedback mechanisms where memory barriers provide feedback to the hardware about when speculative operations should be committed. The hardware monitors these feedback signals and automatically ensures that atomic operations are completed in the correct order, maintaining data integrity while allowing speculative execution to proceed for improved throughput.
Data Source
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AI summary
A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.