Atomic Hydrogen Anneal for Ge and III-V MOS Interfaces
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Solution Overview
Problem
Fermi Level Pinning (FLP) issues in high mobility materials like Ge and III-V compounds used in MOS devices lead to interfacial trap density, hindering performance enhancement beyond the 22nm node and requiring effective passivation methods that do not degrade carrier mobility.
Innovation Solution
A method involving atomic hydrogen anneal, specifically Catalytic Forming Gas Anneal (C-FGA) with noble metals like Pt or Pd, is used to passivate the interface between the gate dielectric and Ge or III-V semiconductor compounds, eliminating the need for interfacial passivation layers and reducing FLP, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interfacial passivation layer (IPL) is deposited between the high mobility III-V compound semiconductor and the gate dielectric layer, then Fermi level pinning is reduced, but electron mobility is significantly reduced and EOT increases
Solution Approach 1:
The patent removes the interfacial passivation layer entirely and instead uses a different approach - depositing the gate dielectric layer directly on the high mobility channel material without an intermediate IPL layer. This extraction of the problematic component eliminates the mobility degradation while maintaining FLP reduction through alternative means such as surface preparation techniques or direct interface engineering.
Solution Approach 2:
The patent changes the deposition parameters and conditions of the gate dielectric layer to achieve direct growth on the high mobility channel material. By adjusting parameters such as deposition temperature, pressure, and composition, the gate dielectric can be deposited directly without forming an IPL, thus maintaining both low FLP and high electron mobility.
2Reliability
If an interfacial passivation layer is deposited to reduce FLP, then Fermi level pinning is avoided, but Equivalent Oxide Thickness increases negatively impacting channel scaling
Solution Approach 1:
The patent extracts and removes the interfacial passivation layer from the device structure, eliminating the extra thickness that contributes to increased EOT. By depositing the gate dielectric directly on the channel material, the overall stack thickness is reduced, enabling better channel scaling while still achieving FLP reduction through direct interface control.
3Reliability
If more than several nanometers of IPL material is applied to reduce FLP, then Fermi level pinning is reduced, but substrate doping is significantly altered
Solution Approach 1:
The patent removes the IPL layer that causes doping alteration, and instead uses direct deposition of the gate dielectric on the high mobility channel material. This eliminates the source of unwanted doping while maintaining FLP reduction through alternative interface engineering approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces FLP, achieves high frequency inversion lift, and creates a field-induced surface quantum well, resulting in low defectivity and high mobility at the channel interface, improving MOS device performance without adding extra thickness or altering substrate doping.
Implementation Method 1
A method involving atomic hydrogen anneal, specifically Catalytic Forming Gas Anneal (C-FGA) with noble metals like Pt or Pd, is used to passivate the interface between the gate dielectric and Ge or III-V semiconductor compounds
Implementation Method 2
Catalytic Forming Gas Anneal (C-FGA) with noble metals like Pt or Pd
Data Source
Figure 1
Figure 2A~2D
Figure 2E~2H
AI summary
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improves the MOS device characteristics such that a MOS device with a quantum well is created.