Programmable Execution Unit Atomic Instruction Feedback
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Solution Overview
Problem
Current graphics processing systems face inefficiencies in executing shader programs due to the need for instruction scheduling, which consumes power and resources, and the requirement to store results in register files for indeterminate times.
Innovation Solution
Implementing a programmable execution unit that executes groups of instructions atomically, allowing results from one instruction to be passed directly to another within the same group, thereby reducing the need for instruction scheduling and register file usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If instruction scheduling is implemented to manage program execution, then program execution control is improved, but power consumption and resource usage increase
Solution Approach 1:
The patent extracts and eliminates the instruction scheduling component from the execution unit. By designing the execution unit to execute instructions in a fixed, predetermined sequence without requiring dynamic scheduling, the power consumption and resource overhead associated with scheduling logic is removed while maintaining execution control through the fixed sequence approach.
Solution Approach 2:
The execution unit is designed to automatically execute instructions in a fixed sequence without requiring external scheduling intervention. The system serves itself by using a simple counter or program counter to automatically advance through instructions, eliminating the need for complex scheduling mechanisms that would increase power consumption.
2Ease of operation
If results are stored in register files for indeterminate times, then data availability is improved, but resource usage increases
Solution Approach 1:
The patent extracts and removes the register file component from the execution unit. By designing the system to pass results directly to the next instruction in the fixed sequence without storing them in register files, the resource usage associated with register files is eliminated while data availability is maintained through direct passing mechanisms.
Solution Approach 2:
Instead of using register files as intermediaries for data storage, the patent implements direct data passing between successive instructions in the fixed sequence. The result of one instruction becomes the input of the next instruction through direct connection, eliminating the need for register file mediation and reducing resource usage.
3Adaptability or versatility
If complex instruction scheduling is implemented, then program execution flexibility is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex instruction scheduling logic from the execution unit. By adopting a fixed sequence execution model, the device complexity associated with scheduling algorithms, priority queues, and resource allocation logic is removed, while program execution flexibility is maintained through the simplicity and predictability of the fixed sequence approach.
4Duration of action of stationary object
If register file access is required for each instruction result, then data persistence is improved, but power consumption increases
Solution Approach 1:
The patent eliminates register file access by implementing direct data passing between successive instructions. The result of one instruction is directly transmitted to the next instruction without being written to or read from the register file, thereby eliminating the power consumption associated with register file access operations while maintaining data persistence through the execution pipeline.
Data Source
AI summary
A programmable execution unit (42) of a graphics processor includes a functional unit (50) that is operable to execute instructions (51). The output of the functional unit (50) can both be written to a register file (46) and fed back directly as an input to the functional unit by means of a feedback circuit (52). Correspondingly, an instruction that is to be executed by the functional unit (50) can select as its inputs either the fed-back output (52) from the execution of the previous instruction, or inputs from the registers (46). A register access descriptor (54) between each instruction in a group of instructions (53) specifies the registers whose values will be available on the register ports that the functional unit will read when executing the instruction, and the register address where the result of the execution of the instruction will be written to. The programmable execution unit (42) executes group of instructions (53) that are to be executed atomically.