Programmable Atomic Transaction Lock Management in Chiplet Systems

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Solution Overview

Problem

Chiplet systems face challenges in efficiently managing memory access and transactions across multiple chiplets, leading to potential bottlenecks and increased latency due to the need for complex interconnects and synchronization mechanisms.

Innovation Solution

The implementation of programmable atomic units within memory controller chiplets that execute programmable atomic transactions, including a termination instruction to ensure exclusive memory access and clear locks, thereby reducing latency and improving transaction throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If programmable atomic transactions are implemented in chiplet systems, then transaction flexibility and functionality are improved, but memory access latency and interconnect congestion increase due to lock management overhead

Engineering Contradiction:
Improvetransaction flexibilityVSAvoidmemory access latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by setting the lock bit immediately when a programmable atomic transaction is initiated, before the actual memory access occurs. This early lock establishment prevents other transactions from attempting to access the same memory location, reducing contention and latency. The lock is cleared only after the transaction completes, ensuring exclusive access throughout the entire operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the lock management functionality from the main transaction execution path by using dedicated lock bits in the memory device that are independently controlled. This separation allows the lock mechanism to operate autonomously, managing access rights without interfering with the core atomic transaction logic, thereby reducing overall system complexity and improving transaction throughput.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If lock mechanisms are used to ensure exclusive memory access, then memory access safety and correctness are improved, but interconnect congestion and transaction throughput are worsened

Engineering Contradiction:
Improvememory access safetyVSAvoidtransaction throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements self-service by enabling each memory device to autonomously manage its own lock bits without requiring external arbitration or coordination. When a transaction needs exclusive access, it directly manipulates the appropriate lock bit in the target memory device, and the memory device itself enforces the lock by blocking other access attempts. This decentralized approach eliminates the need for centralized lock management, reducing interconnect traffic and improving transaction throughput while maintaining memory access safety.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11693690B2Method of completing a programmable atomic transaction by ensuring memory locks are cleared
Publication Date: 2023.07.04 MICRON TECHNOLOGY INC
  • US11693690B2 patent drawing
  • US11693690B2 patent drawing
  • US11693690B2 patent drawing

AI summary

Disclosed is an instruction for a programmable atomic transaction that is executed as the last instruction and that terminates the executing thread, waits for all outstanding store operations to finish, clears the programmable atomic lock, and sends a completion response back to the issuing process. This guarantees that the programmable atomic lock is cleared when the transaction completes. By coupling thread termination with clearing the lock bit, this guarantees that the thread cannot terminate without clearing the lock.