Arbitrating Atomic Memory Operations via Recency and Distance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In distributed systems, multiple nodes competing for atomic memory operations on the same memory module lead to inefficient access arbitration, resulting in performance bottlenecks and increased context switching overhead.

Innovation Solution

A method and apparatus for arbitrating atomic memory operations by determining an ordering based on recency of access and network distance, using a media controller and atomics controller, which issues operations according to predefined arbitration rules and adjusts based on operation rates, allowing for fair and efficient access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multiple nodes compete for atomic memory operations on the same memory module, then memory access fairness is improved, but system performance deteriorates due to arbitration overhead

Engineering Contradiction:
Improvememory access fairnessVSAvoidsystem performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system pre-calculates and stores arbitration priorities for each node based on recency of access and network distance before conflicts occur. When memory access requests are received, the pre-computed priorities are used to determine arbitration outcomes without requiring complex real-time calculations, thus maintaining fairness while improving performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an arbitration logic component that acts as an intermediary between multiple nodes and the memory module. This mediator receives access requests, applies arbitration rules based on recency and network distance, and determines the issuance order, thereby resolving conflicts fairly without degrading overall system performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If arbitration rules are applied to all atomic memory operations, then access fairness is improved, but processing overhead increases

Engineering Contradiction:
Improveaccess fairnessVSAvoidprocessing overhead
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system applies arbitration rules selectively rather than uniformly to all atomic memory operations. By monitoring operation rates and detecting when contention occurs, the system applies full arbitration only when necessary, while allowing faster processing for operations that do not require arbitration, thus reducing overall processing overhead while maintaining fairness when needed.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If context switching is implemented for memory access arbitration, then fairness is improved, but context switching overhead increases

Engineering Contradiction:
Improveaccess fairnessVSAvoidcontext switching overhead
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The arbitration logic serves as an intermediary that handles fairness determination without requiring context switching between operating system threads. By resolving arbitration at the hardware or firmware level through pre-computed priorities and simple comparison logic, the system achieves fair access distribution while avoiding the energy overhead of context switching operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12019566B2Arbitrating atomic memory operations
Publication Date: 2024.06.25 ADVANCED MICRO DEVICES INC
  • US12019566B2 patent drawing
  • US12019566B2 patent drawing
  • US12019566B2 patent drawing

AI summary

Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.