Atomic Memory Device for Coherent Data Modification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The growing gap between processor performance and memory bandwidth leads to increased timing penalties in data retrieval from operating memory, particularly in multi-processor systems where shared data requires coherency control, resulting in costly exclusivity mechanisms.
Innovation Solution
The implementation of an atomic memory device with circuitry that performs data modification operations concurrently with data retrieval, hiding the modification time within the memory access time and eliminating the need for costly exclusivity control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency control mechanisms (locks, semaphores) are implemented to manage shared data access in multi-processor systems, then data coherence and consistency are improved, but system complexity and performance overhead increase
Solution Approach 1:
The patent extracts the coherency control function from the processor level and relocates it to the memory device level. The memory device autonomously manages read-modify-write operations and data coherence without requiring processor-level locks or semaphores, thereby reducing system complexity while maintaining data consistency
Solution Approach 2:
The memory device acts as an intermediary between multiple processors and shared memory. It provides centralized control for data access operations, mediating between read and write requests to ensure coherence without requiring direct processor coordination through complex synchronization mechanisms
2Reliability
If exclusive access control is implemented to prevent concurrent modifications of shared data, then data consistency is improved, but processor stalls and timing penalties increase
Solution Approach 1:
The memory device performs preliminary actions by buffering read data and preparing modified data before actual write operations complete. This allows overlapping of read and write operations in time, reducing processor stalls while maintaining data consistency through controlled sequential execution of read-modify-write cycles
Solution Approach 2:
The patent implements continuous useful action by maintaining buffered read data and queued write operations within the memory device. This allows the system to continue processing without processor stalls, as the memory device internally manages the timing and sequencing of data retrieval and modification operations
3Reliability
If read-modify-write operations are performed sequentially with exclusive access, then data coherence is ensured, but memory access time and system throughput are worsened
Solution Approach 1:
The patent segments the read-modify-write operation into distinct phases: read phase, modification phase, and write phase. By segmenting these operations and implementing them through buffered read data and controlled write cycles in the memory device, the system achieves better throughput while maintaining coherence through sequential execution of segmented operations
Data Source
AI summary
A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.