Atomic Memory Operation Verification via Commutative Selection
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Solution Overview
Problem
Verifying the atomicity of atomic memory operations in computer systems is challenging due to the need for parallel access to shared memory locations, where conventional methods like self-checks and multi-pass consistency checking are intrusive or ineffective, especially when the order of execution affects the end results.
Innovation Solution
Selecting commutative atomic memory operations like ADD, OR, AND, XOR, MIN, or MAX for threads to perform on a shared memory location, ensuring the result is independent of execution order, and using identity operations or swap operations with predetermined values to maintain multi-pass consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-checks or multi-pass consistency checking are used to verify atomic memory operations, then verification capability is provided, but the testing becomes intrusive or ineffective when execution order affects results
Solution Approach 1:
The patent changes the parameter of the atomic memory operation from a general operation to specifically commutative operations (ADD, OR, AND, XOR, MIN, MAX). This parameter change ensures that the operation result is independent of execution order, thereby resolving the contradiction between providing verification capability and avoiding intrusiveness in testing
Solution Approach 2:
The patent performs preliminary selection of commutative operations before executing the atomic memory operations. By pre-determining that only commutative operations will be used, the system ensures that multi-pass consistency checking will be effective without being intrusive, as the commutative property guarantees order-independent results
2Measurement precision
If atomic memory operations are verified in parallel execution, then real-world testing accuracy is improved, but determining correct results becomes difficult when execution order varies
Solution Approach 1:
The patent changes the operational parameter to commutative atomic memory operations, which have the mathematical property that their results are independent of execution order. This allows parallel execution to be tested accurately without the complexity of tracking execution sequences, as the same final result is guaranteed regardless of thread scheduling
Solution Approach 2:
The patent implements a feedback mechanism where the system verifies that the result of commutative atomic memory operations remains consistent across multiple passes. This feedback confirmation validates that the parallel execution produced correct results, eliminating the difficulty of verifying parallel operation outcomes
3Adaptability or versatility
If non-commutative atomic memory operations are tested, then comprehensive coverage is achieved, but multi-pass consistency cannot be guaranteed
Solution Approach 1:
The patent selectively applies commutative operations (ADD, OR, AND, XOR, MIN, MAX) for multi-pass consistency testing while maintaining the ability to test other operations separately. This parameter selection ensures that when multiple passes are executed, the results will be consistent and comparable, providing a stable basis for verification
Data Source
AI summary
A computer-implemented method, computerized apparatus and computer program product for verification of atomic memory operations are disclosed. The method comprising: independently generating for each of a plurality of threads at least one instruction for performing an atomic memory operation of a predetermined type on an allocated shared memory location accessed by the plurality of threads; and, determining an evaluation function over arguments comprising values operated on or obtained in performing the atomic memory operation of the predetermined type on the allocated shared memory location by each of the plurality of threads; wherein the evaluation function is determined based on the atomic memory operation of the predetermined type such that a result thereof is not effected by an order in which each of the plurality of threads performs the atomic memory operation of the predetermined type on the allocated shared memory location.