Atomic Memory Operations on Contended Cache Lines
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Solution Overview
Problem
In shared memory multiprocessor systems, atomic memory operations (AMOs) face performance issues due to delays in cache line coherence protocol state upgrades, leading to 'ping-pong' effects where a cache line is contested between multiple processors, reducing overall system performance.
Innovation Solution
Implement a method where a local cache requests a cache line coherence protocol state upgrade and, if contested, sends the atomic memory operation instruction to a further level of the memory hierarchy closer to the common root of sharing, allowing remote execution to mitigate contention and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache line coherence protocol state upgrade is requested to execute an atomic memory operation locally, then the atomic memory operation can be executed with low latency, but another cache may contest the cache line during the delay period, causing the cache line to bounce between caches and reducing performance
Solution Approach 1:
The system performs preliminary actions by having the lower level memory structure check cache line availability and send a contended cache line message in advance before the atomic memory operation is executed. This preliminary detection and notification allows the local cache to proactively redirect the operation to the lower level memory structure, avoiding the ping-pong effect and reducing contention delays.
2Productivity
If the cache line is kept in the local cache for atomic memory operation execution, then execution speed is improved, but cache line contention between multiple processors causes the cache line to be invalidated and re-fetched repeatedly
Solution Approach 1:
The system implements feedback by having the lower level memory structure monitor cache line availability and send contended cache line messages back to the local cache when contention is detected. This feedback mechanism allows the system to dynamically adjust the execution location of atomic memory operations, ensuring reliable cache line availability while maintaining high processing throughput by avoiding repeated invalidations and re-fetches.
Data Source
AI summary
Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.