Atomic Memory Operation Unit for Multi-Core Processor Bottlenecks
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Solution Overview
Problem
In multiple core processors, atomic memory operations can create bottlenecks due to one-to-many communication across cores, where a core requesting a cache line does not know which other core holds it, leading to inefficient transfer and execution of atomic memory operations.
Innovation Solution
A processor architecture with multiple cores, a bus for data exchange, and a high throughput register that allows atomic memory operations to be executed on a designated core, reducing the need for cache line transfer between cores by setting a high throughput status and forwarding operations via the bus when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If atomic memory operations are performed on a cache line in traditional multi-core processors, then the operations can be executed, but the communication overhead between cores increases and execution speed decreases
Solution Approach 1:
The patent segments the atomic memory operation handling by introducing a dedicated atomic memory operation unit that is separate from the traditional load store unit. This segmentation allows atomic operations to be processed independently with specialized handling, reducing the communication overhead and improving execution speed by dedicating specific hardware resources to this function.
Solution Approach 2:
The patent introduces a high throughput register as an intermediary component between the load store unit and the atomic memory operation unit. This intermediary facilitates efficient data transfer and status indication, allowing the system to manage atomic operations with reduced communication overhead between processor cores while maintaining high execution speed.
2Productivity
If cache line transfer is used for atomic memory operations across multiple cores, then operations can be performed on shared memory, but the one-to-many communication creates a bottleneck
Solution Approach 1:
The patent implements preliminary action by having the high throughput register pre-indicate when a processor core is ready to handle atomic memory operations with high throughput capability. This allows other cores to forward atomic operations to the designated core proactively, rather than waiting for cache line transfers, thereby reducing transfer time and increasing overall productivity of atomic memory operations.
Solution Approach 2:
The patent uses copying by forwarding atomic memory operation requests through the inter-core bus to a designated processor core that has the high throughput status set. Instead of transferring the actual cache line data between cores, the system copies only the operation request, which is then executed by the designated core, significantly reducing the time required for cross-core atomic operations.
3Ease of operation
If a core requests a cache line without knowing which core holds it, then memory access can be attempted, but the uncertainty leads to inefficient transfer protocols
Solution Approach 1:
The patent implements feedback through the high throughput register, which provides real-time status information to other processor cores about which core is currently capable of handling atomic memory operations with high throughput. This feedback mechanism eliminates the uncertainty in the memory access request process, allowing cores to directly forward atomic operations to the appropriate destination without inefficient probing or broadcasting, thereby improving transfer efficiency while maintaining ease of operation.
Data Source
AI summary
A processor comprising multiple processor cores and a bus for exchanging data between the multiple processor cores is disclosed. Each of the multiple processor cores includes: at least one processor register; a cache for storing at least one cache line of memory; a load store unit for executing a memory command to exchange data between the cache and the at least one processor register; an atomic memory operation unit for executing an atomic memory operation on the at least one cache line of memory; and a high throughput register for storing a status indicating a high throughput or a normal status. The load store unit is operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core if the atomic memory operation status is the high throughput status using the bus.