Atomic Non-Volatile Memory Data Transfer via Shared Bus
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Solution Overview
Problem
Flash memory devices face limitations in endurance due to limited programming and erasing cycles, necessitating optimized memory management and data transfer processes to enhance performance and reduce power consumption.
Innovation Solution
A storage device configuration with a controller, multiple non-volatile memory dies, and a shared bus for atomic data transfers, including data reading, strobe generation, and error correction, to efficiently transfer data between memory dies while optimizing memory management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is transferred between memory dies using traditional read-write operations through the controller, then data transfer can be completed, but power consumption increases and transfer speed decreases
Solution Approach 1:
The patent introduces a shared bus as an intermediary communication channel between memory dies, enabling direct data transfer without routing through the controller. This mediator allows memory dies to exchange data autonomously, reducing the power consumption associated with controller operations while significantly increasing transfer speed through direct peer-to-peer communication.
Solution Approach 2:
The patent segments the memory system into independent memory dies that can operate autonomously. Each memory die functions as an independent unit capable of generating and responding to strobe signals, allowing parallel operations and direct communication between segments. This segmentation eliminates the bottleneck of centralized controller processing, thereby improving both power efficiency and transfer speed.
2Reliability
If traditional memory management processes are used, then data can be accessed, but endurance is reduced due to limited programming and erasing cycles
Solution Approach 1:
The patent implements preliminary action by performing data transfer and validation operations between memory dies before committing to full programming or erasing cycles. The atomic transfer mechanism allows data to be staged and verified in transit, enabling early detection of transfer issues and reducing unnecessary wear-inducing operations on the memory cells.
Solution Approach 2:
The patent incorporates feedback mechanisms through strobe signal generation and recognition. The sending memory die generates a strobe signal that is recognized by the receiving die, creating a feedback loop that confirms successful data transfer. This feedback system enables real-time monitoring of transfer integrity, reducing the need for re-operations and thereby improving endurance.
3Productivity
If data transfer operations are optimized for speed, then performance improves, but reliability of data transfer decreases
Solution Approach 1:
The shared bus acts as a controlled intermediary that enforces proper signaling protocols between memory dies. The bus infrastructure includes built-in mechanisms for strobe signal generation and recognition, which automatically ensure data validity during high-speed transfers. This mediator maintains reliability by preventing race conditions and ensuring proper timing without sacrificing transfer speed.
Solution Approach 2:
The memory dies perform self-service validation through the strobe signal mechanism. The sending die automatically generates the strobe signal as part of the transfer process, and the receiving die autonomously recognizes and validates the data upon receiving the strobe. This self-service approach ensures data integrity through distributed validation rather than centralized checking, maintaining both high performance and reliability.
Data Source
AI summary
The various implementations described herein include systems, methods and/or devices used to transfer data within a storage device. In one aspect, a method includes reading data from a first non-volatile memory device to a shared bus, where the shared bus couples the first non-volatile memory device to a second non-volatile memory device and to the controller, and where the first non-volatile memory device is on a first die and the second non-volatile memory device is on a second die, distinct from the first die. The method further includes, in conjunction with reading the data from the first non-volatile memory device to the shared bus, generating a data strobe at the first non-volatile memory device; and, in response to receiving the data strobe at the second non-volatile memory device, transferring the data from the shared bus to the second non-volatile memory device.