Atomic Operations in Compute-Near-Memory Systems
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Solution Overview
Problem
Current computer architectures face performance and capacity constraints due to the time and energy required for data movement between processors and memory, limiting advancements beyond transistor scaling.
Innovation Solution
The implementation of compute-near-memory (CNM) systems, which integrate processors with memory or data storage components, utilizing a custom compute fabric and network structures to facilitate low-latency operations and support atomic operations, enabling efficient data access and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved between processors and memory using conventional bus architecture, then system compatibility and ease of manufacture are maintained, but performance and capacity are constrained due to time and energy requirements
Solution Approach 1:
The system segments memory access operations into atomic operations that can be executed independently and concurrently. Each atomic operation is a discrete unit that can be processed by multiple compute elements simultaneously, dividing the overall data access workload into smaller, parallelizable units that reduce total access time
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling multiple compute elements to access and operate on memory locations simultaneously through atomic operations. This multi-dimensional access pattern breaks the conventional sequential access model, allowing throughput to scale with the number of compute elements rather than being bottlenecked by single-bus bandwidth
2Productivity
If data is moved between processors and memory using conventional bus architecture, then system simplicity is maintained, but energy consumption increases
Solution Approach 1:
Atomic operations enable compute elements to perform data manipulation directly at memory locations without requiring repeated data movement between processors and memory. The atomic operation units execute computations in-place, allowing data to serve itself through self-contained operations that combine data access and processing in a single energy-efficient step
Solution Approach 2:
The patent merges data access and data processing into unified atomic operations. Instead of separate read-modify-write cycles that consume multiple bus transactions, atomic operations combine these functions into single integrated units, reducing the total number of data movement operations and associated energy consumption
3Reliability
If atomic operations are implemented in hardware, then race conditions are prevented and reliability is improved, but device complexity increases
Solution Approach 1:
Atomic operation units serve as intermediary hardware components between compute elements and memory. These specialized units handle the complexity of atomic operations (lock management, conflict resolution, serialization) internally, shielding the rest of the system from complexity while ensuring reliable race-condition-free execution. The intermediaries translate high-level atomic operation requests into low-level coordinated memory access sequences
Data Source
AI summary
Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.