Atomic Permission Bit for Cross-Unit Memory Atomicity
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Solution Overview
Problem
In computer systems with unified virtual memory architecture, atomic operations across multiple processing units, such as CPUs and GPUs, are not ensured to be indivisible, leading to potential inconsistencies and inefficiencies due to simultaneous access, and existing solutions like bus locking degrade system performance.
Innovation Solution
A method is introduced where a processing unit initiates an atomic operation by activating the atomic permission bit in its page table entry, denying access to other units, ensuring exclusive access to the memory page during the operation without using bus locks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If atomic operations are handled on a localized basis with specialized hardware in each processing unit, then atomic operations within a single processing unit are ensured to be indivisible, but atomicity is not ensured across multiple processing units accessing shared memory
Solution Approach 1:
The patent merges the atomic operation handling across multiple processing units by introducing a unified page table mechanism that spans CPU and GPU address spaces. The page table includes an atomic permission bit that is universally recognized by both CPU and GPU, creating a combined atomicity guarantee across heterogeneous processing units that previously operated independently.
Solution Approach 2:
The page table serves as an intermediary structure between processing units and memory, mediating atomic operations through the atomic permission bit. This intermediary mechanism coordinates access requests from multiple processing units without requiring direct communication between them, resolving the atomicity problem through a centralized control structure.
2Reliability
If a lock signal is asserted on the bus to prevent other processing units from accessing memory during atomic operations, then atomicity across processing units is ensured, but other bus processes are blocked leading to system performance degradation
Solution Approach 1:
Instead of applying a global bus lock that affects all memory operations, the patent applies atomic protection locally and selectively through the page table's atomic permission bit. This local quality approach allows atomic operations to be protected without blocking non-atomic memory accesses, maintaining system throughput while ensuring atomicity where needed.
Solution Approach 2:
The patent implements partial atomic protection by using the atomic permission bit in the page table to selectively enable atomic semantics only for specific memory pages that require it, rather than applying atomic guarantees to all memory operations. This partial action approach maintains high system performance while providing atomicity where required.
3Productivity
If simultaneous access to shared memory pages is permitted across multiple processing units, then system throughput is maintained, but atomic operations may result in unexpected or unintended results due to race conditions
Solution Approach 1:
The system performs preliminary classification of memory pages by setting the atomic permission bit in the page table before atomic operations occur. This preliminary action pre-configures the memory protection semantics, allowing the memory management unit to automatically enforce atomicity without runtime negotiation or blocking, thus maintaining throughput while ensuring correctness.
Data Source
AI summary
One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.