Atomic Processing Engine for Shared Memory Lock Contention
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Solution Overview
Problem
In multi-threaded and multicore processors, shared data structures can lead to bottlenecks due to lock mechanisms, which adversely affect system throughput and can result in deadlocks, requiring significant programming effort to alleviate these issues.
Innovation Solution
An atomic processing engine (APE) is coupled to processor cores, receiving commands and performing operations on shared memory locations, including complex atomic commands, while autonomously managing locks to avoid contention and reduce programming complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lock mechanisms are used to limit access to shared data elements, then data consistency is maintained, but system throughput is adversely affected and deadlocks may occur
Solution Approach 1:
The patent segments the locking mechanism into fine-grained sections at the programming level, allowing different portions of a data structure to be locked independently. This segmentation enables concurrent access to different sections, thereby maintaining data consistency while improving system throughput by reducing contention on shared resources.
Solution Approach 2:
The patent introduces an intermediary mechanism (fine-grained locking section) between the lock and the shared data structure. This intermediary allows for more granular control over access, enabling multiple threads to access different portions of the data structure simultaneously, thus reducing deadlocks and improving throughput while maintaining consistency.
2Productivity
If fine-grained sections are constructed to alleviate the lock bottleneck, then system throughput is improved, but significant programming time and effort are required
Solution Approach 1:
The patent enables the system to automatically manage fine-grained locking sections without requiring manual intervention. The compiler or runtime system automatically divides the data structure into lockable sections and manages the locking/unlocking operations, thereby improving system throughput while eliminating the need for programmers to manually construct fine-grained sections, thus reducing programming complexity.
Solution Approach 2:
The patent performs preliminary actions by automatically identifying and dividing data structures into fine-grained sections before runtime. This preliminary segmentation is done by the compiler or system, so that during execution, the fine-grained locking mechanism is already in place and ready to improve throughput without requiring programmers to spend time constructing these sections manually.
3Reliability
If manual fine-grained locking is implemented, then deadlock is reduced, but programming effort and time increase significantly
Solution Approach 1:
The patent implements self-service by enabling the system to automatically manage fine-grained locking sections. The compiler or runtime system automatically identifies potential deadlock scenarios and manages the locking/unlocking operations accordingly, thereby reducing deadlocks while eliminating the need for programmers to manually implement complex locking logic, thus saving programming time.
Solution Approach 2:
The patent incorporates feedback mechanisms where the system monitors lock acquisition and release patterns to dynamically adjust locking strategies. This feedback allows the system to automatically prevent deadlocks by detecting potential conflicts and managing lock ordering, thereby improving reliability while reducing the programming effort needed to implement deadlock avoidance manually.
Data Source
AI summary
A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.