Atomic Queue Management Unit for Parallel Data Access
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Solution Overview
Problem
Managing the insertion and deletion of data in shared data structures by multiple entities in parallel computing systems is challenging due to contention and performance bottlenecks, with existing solutions like locks and prefix-sums adding complexity and overhead.
Innovation Solution
Implementing an atomic queue management unit in the memory controller to ensure atomicity of enqueue and dequeue operations, using system calls to allocate and register atomic queues, and utilizing non-cacheable memory spaces to prevent processor caching, allowing for efficient access and metadata management across multiple threads and processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If locks are used to coordinate manipulations of shared data structures, then atomicity and data integrity are ensured, but system performance deteriorates due to contention and overhead
Solution Approach 1:
The patent extracts the coordination function from software locks and relocates it to hardware-level memory controllers. The memory controller independently manages queue metadata and coordinates access between multiple processing units, eliminating the need for software locks and their associated contention overhead while maintaining atomicity guarantees
Solution Approach 2:
The memory controller acts as an intermediary between multiple processing units and shared data structures. It receives operations from multiple threads, automatically serializes access to queue metadata, and returns results to processing units, thereby ensuring data integrity without requiring processing units to implement complex locking protocols
2Productivity
If prefix-sums and pre-calculation of offsets are used for thread access coordination, then parallel access is enabled, but device complexity and software overhead increase
Solution Approach 1:
Each processing unit independently generates operations with unique identifiers, and the memory controller automatically routes these operations to the appropriate queues using its internal coordination logic. This self-service approach eliminates the need for threads to pre-calculate offsets or implement complex coordination algorithms, reducing software overhead while maintaining parallel access capability
3Speed
If queue metadata is cached in processor cache, then access speed improves, but atomicity and consistency are compromised due to caching coherence issues
Solution Approach 1:
Instead of caching metadata in processor caches (which causes coherence problems), the patent inverts the approach by placing metadata in non-cacheable memory regions. The memory controller then becomes the authoritative source for metadata, ensuring that all processing units see consistent, up-to-date information without caching coherence issues, while still providing fast access through the memory controller's internal buffers
Data Source
AI summary
Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.