Atomic Scale Device Fabrication Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for fabricating atomic scale devices face challenges in achieving accurate alignment of macroscopic electrical contacts and control gate electrodes with buried STM-fabricated structures, particularly due to high temperature anneal constraints and surface contamination, which limits the precision and longevity of registration markers.
Innovation Solution
A method involving the use of STM or SEM to pattern regions for electrically active components, followed by encapsulation with semiconductor material, allowing for ex-situ imaging with optical or electron microscopes to align surface conducting elements with buried components, achieving alignment accuracies down to 50 nm through a combination of STM, SEM, and electron beam lithography techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature anneal is used to prepare atomically flat Si surfaces, then surface quality is improved, but registration markers deteriorate and alignment precision is reduced
Solution Approach 1:
The patent applies preliminary action by etching registration markers to a sufficient depth (300 nm) before the high temperature anneal process. This pre-positioning ensures that the markers survive the subsequent thermal processing and surface preparation steps, maintaining alignment precision throughout the fabrication sequence.
2Duration of action of stationary object
If registration markers are etched deeply to survive high temperature anneal, then marker durability is improved, but alignment precision is reduced to 500 nm
Solution Approach 1:
The patent segments the alignment system into multiple hierarchical levels: deep etched markers (300 nm) for surviving high temperature anneal and providing robust reference points, combined with additional alignment markers and imaging techniques (optical microscope, STM, SEM) for achieving sub-500 nm precision in subsequent steps.
Solution Approach 2:
The patent introduces an intermediary imaging and measurement system (optical microscope, STM, SEM) that mediates between the deep etched markers and the final alignment process. This intermediary system allows precise measurement and adjustment based on the marker positions, achieving alignment accuracies better than 500 nm despite the deep etching.
3Manufacturing precision
If STM is used for atomic scale patterning, then patterning precision is improved, but device complexity increases due to UHV requirements
Solution Approach 1:
The patent segments the fabrication process into distinct environmental zones: UHV environment for atomic-scale STM patterning steps, and ex-situ ambient environment for subsequent processing steps. This segmentation allows each process to occur in its optimal environment, maintaining atomic-scale precision while enabling complex multi-step fabrication.
Solution Approach 2:
The patent applies the nested doll principle by embedding the atomic-scale device structure created in UHV within a larger encapsulation structure that can be processed ex-situ. The device is encapsulated in silicon, creating a nested configuration where the sensitive UHV-fabricated structure is protected within a robust outer structure that can withstand subsequent processing in ambient conditions.
4Adaptability or versatility
If multiple processing steps are performed ex-situ, then device functionality is improved, but alignment accuracy deteriorates due to cumulative errors
Solution Approach 1:
The patent implements feedback by using imaging systems (optical microscope, STM, SEM) to continuously monitor and measure the positions of alignment markers and device features throughout the ex-situ processing steps. This feedback information is used to adjust and correct alignment in subsequent steps, compensating for cumulative errors and maintaining high alignment accuracy despite multiple processing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of highly planar atomic scale multi-terminal devices with improved alignment accuracy, increased yield, and reduced thermal budget, allowing for reliable electrical contact formation without the need for ex-situ ohmic contact metallisation anneal.
Implementation Method 1
opening one or more regions of a mask on a semiconductor surface using a scanning tunnelling microscope (STM) tip capable of atomic precision
Implementation Method 2
Using a SEM to form an image of at least one of the registration markers and the tip of a STM
Implementation Method 3
imaging the components of the device encapsulated below the surface using an optical or electron microscope
Implementation Method 4
Depositing a metal layer onto the silicon surface using either optical or electron beam lithography
Implementation Method 5
encapsulating the components of the device with more of the semiconductor
Data Source
AI summary
This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.