Programmable Atomic Unit Thread Self-Scheduling for Memory Latency
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Solution Overview
Problem
Chiplet systems face complexity in scheduling threads due to resource contention, particularly with memory requests, which can lead to increased processor complexity and die area requirements when using traditional hazard tracking methods.
Innovation Solution
Implementing self-scheduling threads by using thread identifiers to manage thread execution and resource availability, where thread IDs are enqueued only when resources are available, and removed upon completion of memory requests, allowing instructions to determine when resources are cleared for reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hazard tracking methods are used to manage thread scheduling, then thread execution control is achieved, but processor complexity and die area requirements increase
Solution Approach 1:
The patent extracts the hazard tracking functionality from the processor core and relocates it to the instruction itself. Thread IDs are embedded directly in instructions, and hazard tracking is performed by examining these embedded IDs rather than maintaining separate processor-wide hazard tables. This extraction reduces processor complexity while maintaining execution control.
Solution Approach 2:
The patent uses thread IDs as copies of thread identity information that are propagated through the instruction stream. Instead of maintaining complex hazard state in the processor, simple thread ID copies are attached to instructions and used for scheduling decisions, significantly reducing the complexity of hazard tracking mechanisms.
2Reliability
If traditional hazard tracking methods are used to manage thread scheduling, then thread execution control is achieved, but die area requirements increase
Solution Approach 1:
The hazard tracking data structures are extracted from the processor core and replaced with compact thread ID fields within instructions. This extraction eliminates large hazard tables and associated control logic, thereby reducing die area while maintaining thread execution control capabilities.
Solution Approach 2:
The patent uses simple, disposable thread ID tags attached to instructions rather than persistent, complex hazard state structures. These thread IDs are created, used for scheduling decisions, and then discarded, replacing expensive long-lived hazard tracking data structures with cheap short-lived identifiers.
3Device complexity
If self-scheduling threads are implemented, then processor complexity and die area are reduced, but throughput may be affected by memory latency
Solution Approach 1:
The patent performs preliminary actions by pre-fetching and speculatively executing instructions from multiple threads before hazards are resolved. Thread IDs are attached to instructions in advance, and the processor speculatively proceeds with execution while maintaining the ability to rollback or reorder if hazards are detected, thereby maintaining throughput despite memory latency.
Solution Approach 2:
The patent maintains continuity of useful action by keeping multiple threads in flight simultaneously. When one thread encounters memory latency, other threads continue executing, ensuring the processor remains productive. The self-scheduling mechanism using thread IDs allows seamless switching between threads to maintain continuous useful work.
Data Source
AI summary
Devices and techniques for threads in a programmable atomic unit to self-schedule are described herein. When it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.