Programmable Atomic Trap Notification for Chiplet Exception Handling
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Solution Overview
Problem
In chiplet systems, programmable atomic transactions executed by memory controllers often encounter exceptions without the memory controller knowing which process triggered the fault, leading to inefficient handling and increased overhead due to constant flag polling by the operating system.
Innovation Solution
Implementing a mechanism where programmable atomic units send a response to the calling processor, allowing the processor to handle exceptions directly, thereby reducing overhead and enabling efficient fault management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller polls flags constantly to detect exceptions, then exception detection capability is maintained, but system overhead increases and processing efficiency decreases
Solution Approach 1:
The memory controller autonomously detects exceptions through status registers and automatically sends trap notifications to the processor without requiring the processor to constantly poll flags. This self-service mechanism eliminates wasted polling cycles while maintaining reliable exception detection.
Solution Approach 2:
The system implements a feedback loop where the memory controller monitors its own status registers, detects exception conditions, and actively notifies the processor. This feedback mechanism ensures exceptions are detected reliably while avoiding the inefficiency of continuous processor polling.
2Measurement precision
If the operating system polls flags constantly to identify triggering processes, then exception identification accuracy is maintained, but system overhead increases
Solution Approach 1:
The memory controller acts as an intermediary that bridges the exception detection function between the hardware and operating system. It monitors status registers, identifies exceptions with precise process information, and communicates this directly to the processor, eliminating the need for the operating system to poll flags and reducing overall system complexity.
3Productivity
If programmable atomic units execute transactions without direct processor oversight, then transaction throughput increases, but exception handling efficiency decreases
Solution Approach 1:
The memory controller prepares exception trap notifications in advance by monitoring status registers during transaction execution. When an exception occurs, the notification is already prepared and can be sent immediately to the processor, reducing exception handling time while maintaining high transaction throughput.
Data Source
AI summary
Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).