Programmable Atomic Unit Virtualization for Shared Chiplet Memory Control
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Solution Overview
Problem
Existing chiplet systems face challenges in efficiently executing customized, high-performance atomic transactions due to limitations in inter-chiplet communication and resource sharing, particularly in managing programmable atomic units that are shared by multiple processes.
Innovation Solution
Implementing a memory controller chiplet with programmable atomic units (PAUs) that execute customized atomic transactions, utilizing a Chiplet Protocol Interface (CPI) for flexible inter-chiplet communication and credit-based flow control, along with a programmable atomic unit (PAU) capable of executing user-defined transactions, and a method for registering and virtualizing these transactions through a unique identifier system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chiplet systems use established networks for inter-chiplet communication, then system modularity and ease of manufacture are improved, but communication latency and congestion increase
Solution Approach 1:
The patent segments the communication system into multiple virtual channels within the inter-chiplet network, allowing different types of traffic (atomic transactions, memory access, I/O operations) to be routed through dedicated virtual channels. This segmentation reduces congestion and latency by preventing different traffic types from interfering with each other, while maintaining the modular chiplet architecture.
Solution Approach 2:
The patent introduces a network-on-chip (NoC) intermediary layer that manages communication between chiplets. This NoC includes virtual channel multiplexers and credit-based flow control mechanisms that mediate traffic between chiplets, reducing congestion and latency while preserving the modular design benefits.
2Device complexity
If atomic transactions are implemented through existing memory controller functionality, then device complexity is reduced, but transaction customization and performance are limited
Solution Approach 1:
The patent implements programmable atomic units (PAUs) that can be dynamically configured to execute different atomic transaction types. The PAUs use a programmable instruction set that allows the same hardware unit to adapt to different atomic operation requirements (compare-and-swap, fetch-and-add, etc.), providing customization without requiring separate dedicated hardware for each transaction type.
Solution Approach 2:
The patent changes the operational parameters of the atomic units by providing a programmable instruction set that modifies the behavior of the PAUs. Different instructions configure the PAUs to perform different atomic operations, allowing transaction customization through parameter changes rather than structural modifications.
3Productivity
If multiple processes share programmable atomic units, then resource utilization improves, but identifier management and transaction routing complexity increase
Solution Approach 1:
The patent creates a universal identifier mapping mechanism that allows the same PAU to serve multiple processes. The system uses a translation layer that maps process-specific atomic unit identifiers to physical PAU identifiers, enabling any process to access any PAU through a unified interface while the translation layer handles the complexity of resource allocation and conflict resolution.
Data Source
AI summary
Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.