Programmable Atomic Unit Instruction Memory Pre-loading

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Solution Overview

Problem

The existing solutions for executing programmable atomic transactions in chiplet systems suffer from significant latency due to the need to load instructions from a memory controlled by the memory controller during the transaction.

Innovation Solution

Storing instructions for programmable atomic transactions in the memory of the programmable atomic unit prior to execution, allowing them to be ready for immediate execution when the transaction is requested, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If instructions are loaded from memory controller during transaction execution, then the system can maintain modular chiplet architecture, but transaction latency increases significantly

Engineering Contradiction:

Improvemodular chiplet architectureVSAvoidtransaction latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-loading transaction instructions into the programmable atomic unit's local memory before the transaction is executed. This allows the instructions to be immediately available when needed, eliminating the latency that would result from loading them from the memory controller during transaction execution.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies segmentation by dividing the instruction storage function between the memory controller and the programmable atomic unit's local memory. This segmentation allows the critical instruction retrieval operation to occur locally within the atomic unit rather than requiring communication with the memory controller, thus reducing latency while maintaining the overall modular architecture.

Inventive Principle:

Principle #1Segmentation

2Loss of time

If instructions are pre-loaded in programmable atomic unit memory, then transaction execution latency is reduced, but memory organization complexity increases

Engineering Contradiction:

Improvetransaction execution latencyVSAvoidmemory organization complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses preliminary action to pre-load instructions into the programmable atomic unit's memory before execution. This approach reduces execution latency by having instructions ready in advance, while the memory organization complexity is managed through structured partitioning and control mechanisms.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies dynamics by making the instruction memory content configurable and changeable. The memory can be dynamically loaded with different instruction sets based on the specific atomic transaction type that needs to be executed, allowing the system to adapt to different transaction requirements while maintaining a unified memory structure.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250156098A1Method of organizing a programmable atomic unit instruction memory

Publication Date: 2025.05.15 MICRON TECHNOLOGY INC

AI summary

Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.