Atomic Write Coherency in Flash Storage via S-Journal
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Solution Overview
Problem
Conventional flash-based data storage devices face inefficiencies in managing atomic write commands, particularly in detecting incomplete writes, garbage collection, and write amplification, due to the inability to efficiently handle power cycles and the need for large logical-to-physical mapping tables that require significant volatile memory, leading to performance issues and increased complexity.
Innovation Solution
The implementation of a System Journal (S-Journal) and atomic sequence numbers to maintain coherency of the logical-to-physical address translation map, allowing for efficient detection of incomplete atomic write commands and reduced write amplification by using non-volatile buffers and separate mapping for atomic write operations, enabling power-safe data storage and recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large L2P map table is used to map logical entries to physical address locations, then address translation capability is improved, but volatile memory requirements and system complexity increase
Solution Approach 1:
The patent segments the large L2P map table into multiple smaller sub-mapping tables organized in a hierarchical structure. Each sub-table manages a portion of the address space, allowing the system to handle large address translation requirements without requiring a single large volatile memory table. This segmentation reduces the memory burden on the controller and distributes the complexity across multiple manageable components.
Solution Approach 2:
The patent introduces a hierarchical dimension to the address translation system by organizing sub-mapping tables in levels. Instead of a flat single-level L2P table, the system uses multi-level hierarchical mapping where higher-level tables map to lower-level tables, which in turn map to physical addresses. This dimensional change allows efficient address translation with reduced memory requirements.
2Reliability
If the entire L2P map table is saved with each write operation, then data integrity is improved, but write amplification increases
Solution Approach 1:
The patent extracts only the necessary portions of the L2P map table that are affected by each write operation, rather than saving the entire table. By identifying and extracting only the specific sub-mapping tables or entries that need updating, the system maintains data integrity for changed data while avoiding redundant writes of unchanged portions, thereby reducing write amplification.
Solution Approach 2:
The patent applies partial action by updating only the specific portions of the mapping structure that are affected by each write operation. Instead of performing a complete table save (excessive action), the system selectively updates only the necessary sub-mapping tables or entries, maintaining sufficient data integrity while minimizing unnecessary write operations to flash memory.
3Adaptability or versatility
If random writes are performed in flash memory, then data storage flexibility is improved, but the number of erase cycles increases
Solution Approach 1:
The patent performs preliminary actions by pre-managing flash memory blocks through wear leveling and proactive garbage collection. Before random writes are performed, the system prepares appropriate blocks by wearing them evenly and clearing invalid data, allowing flexible random write operations without immediately increasing erase cycles. This preliminary preparation reduces the impact of subsequent write operations on overall erase cycle consumption.
Data Source
AI summary
Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.