ATPG Circuit Verification Logic Cone Segmentation
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Solution Overview
Problem
The complexity of modern chip circuits leads to increased verification time and reduced efficiency in automatic test pattern generation (ATPG) methods, particularly due to the lengthy time required to generate conjunctive normal forms (CNFs) for large circuits.
Innovation Solution
The proposed method involves determining a to-be-detected first logic cone from the fan-out logic cone and a second logic cone from the fan-in logic cone, generating a CNF based on these cones, and using the CNF to detect faults in the target line, thereby reducing the complexity and time of CNF generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SAT-based ATPG testing is used to detect each line in the circuit under test, then detection completeness is improved, but verification time increases significantly
Solution Approach 1:
The patent segments the circuit under test into multiple logic cones, each centered around a target line. Instead of generating a single CNF for the entire circuit, the method generates separate CNFs for each logic cone and processes them independently. This segmentation allows parallel processing and reduces the time complexity of CNF generation while maintaining comprehensive fault detection coverage across all lines in the circuit.
2Measurement precision
If CNF is generated for the entire fan-in and fan-out regions, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by focusing CNF generation on localized regions (logic cones) rather than the entire circuit. Each logic cone is defined by its fan-in and fan-out regions relative to a target line, creating a localized analysis scope. This approach maintains detection accuracy for the target line while reducing the overall complexity of CNF generation by limiting the scope to relevant local regions only.
Solution Approach 2:
The method extracts and processes only the necessary fan-in and fan-out regions for each target line, separating them from the rest of the circuit. By taking out these specific regions to form logic cones, the patent reduces the complexity of CNF generation while preserving the detection accuracy needed for fault identification in the target line.
3Quantity of substance
If serial calculation is used for CNF generation in large circuits, then resource usage is reduced, but productivity decreases
Solution Approach 1:
The patent divides the circuit into multiple independent logic cones that can be processed in parallel. Each logic cone corresponds to a target line and its associated fan-in/fan-out regions. This segmentation enables simultaneous CNF generation and SAT solving for multiple cones, significantly improving verification efficiency and productivity while maintaining manageable resource usage for each individual cone.
Data Source
AI summary
An automatic test pattern generation-based circuit verification method, comprises determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first conjunctive normal form (CNF) based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.