ATPG Test Pattern Flow Using TD-Covered SA Fault Filtering
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Solution Overview
Problem
Modern digital circuits with millions of gates and flip-flops require automatic test pattern generators (ATPG) to efficiently generate test patterns reflecting various fault models, but existing methods struggle to reduce the number of test patterns while maintaining test coverage.
Innovation Solution
A method and device that generate test patterns by first identifying detectable transition delay (TD) faults and stuck-at (SA) faults, using a TD ATPG module to create a pre-detected fault list (PDFL), and then generating SA test patterns only for nodes not covered by TD test patterns, reducing duplicate generation and overall pattern count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test patterns are generated for both TD faults and SA faults, then comprehensive fault coverage is achieved, but the total number of test patterns increases
Solution Approach 1:
The patent applies preliminary action by first generating TD test patterns and identifying SA faults that are already detectable through these patterns. This preliminary detection allows the subsequent SA fault detection phase to focus only on undetected faults, thereby reducing the total number of test patterns needed while maintaining comprehensive coverage
Solution Approach 2:
The patent merges the TD fault detection and SA fault detection processes into a unified test pattern generation flow. By integrating the PDFL generation from TD testing into the SA fault detection workflow, the system combines both fault model detections into a coordinated process that minimizes redundant test patterns
2Reliability
If test patterns are generated for all possible SA faults, then complete SA fault coverage is achieved, but redundant patterns are created for faults already detectable through TD patterns
Solution Approach 1:
The patent extracts and removes SA faults that are already detectable through TD test patterns by generating a PDFL during the TD fault detection phase. This extraction prevents redundant SA fault pattern generation, as the SA ATPG module skips patterns for faults already listed in the PDFL
Solution Approach 2:
The patent applies partial action by generating SA test patterns only for the subset of SA faults that are not already detectable through TD patterns. Instead of generating patterns for all possible SA faults, the system performs partial detection focused on undetected faults, thereby avoiding excessive or redundant test pattern generation
Data Source
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AI summary
A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.