ATPG Pattern Generation for TD and Stuck-At Fault Reduction
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Solution Overview
Problem
Modern digital circuits with millions of gates and flip-flops require efficient test pattern generation technology to address various fault models, particularly for transition delay and stuck-at faults, but existing methods are inefficient in reducing the number of test patterns while maintaining test coverage.
Innovation Solution
A method and device for generating test patterns that involve obtaining design data to determine detectable test patterns, thereby reducing the number of test patterns required for a test pattern generating device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ATPG methods are used to generate test patterns for both transition delay faults and stuck-at faults independently, then comprehensive fault coverage is achieved, but the number of test patterns becomes excessively large
Solution Approach 1:
The patent merges the test pattern generation processes for transition delay faults and stuck-at faults into a unified framework. The TD ATPG module and SA ATPG module share common components including the circuit model, fault list management, and test pattern generation engine. This integration allows the system to generate test patterns that can detect both TD faults and SA faults simultaneously, reducing the total number of test patterns required while maintaining comprehensive fault coverage.
Solution Approach 2:
The test pattern generating device is designed with multi-functionality to handle multiple fault models (both transition delay faults and stuck-at faults) within a single system. The unified fault list and shared generation logic enable the device to perform multiple detection functions using a reduced set of test patterns, eliminating the need for separate independent generation processes for each fault type.
2Reliability
If separate test pattern generation is performed for transition delay faults and stuck-at faults, then each fault type is thoroughly detected, but the generation time and computational resources increase
Solution Approach 1:
The patent combines the test pattern generation operations for TD faults and SA faults into a single integrated process. The unified ATPG system processes both fault types concurrently or in an optimized sequence, sharing computational resources and intermediate results. This merging eliminates redundant computations and reduces the total generation time compared to performing separate independent generation processes for each fault type.
Data Source
AI summary
A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.