ATPG Test Circuit Frequency Measurement
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Solution Overview
Problem
Current Automatic Test Pattern Generation (ATPG) circuits are unable to test the frequency of generated test clock signals, requiring additional clock monitor circuits that consume extra area and complicate routing, leading to potential malfunctions in test circuitry.
Innovation Solution
A test circuit that includes a scan chain and a clock circuit capable of operating in both clock generation and frequency determination modes, allowing it to pass and count test clock signals, eliminating the need for separate clock monitor circuits by integrating frequency testing within the ATPG circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate clock monitor circuit is used to test the frequency of generated clock signals, then the frequency testing capability is improved, but the circuit area and routing complexity increase
Solution Approach 1:
The patent merges the clock monitor functionality into the ATPG circuit by utilizing the existing scan chain and flip-flops. The scan chain is configured to capture clock signal transitions, and the ATPG circuit itself performs frequency measurement by counting clock cycles during the capture phase, eliminating the need for a separate clock monitor circuit and reducing overall circuit area.
Solution Approach 2:
The ATPG circuit is designed to perform multiple functions: both test pattern generation and clock frequency monitoring. The scan chain serves dual purposes by capturing both test data and clock signal transitions. This multi-functionality allows the same hardware resources to be used for both ATPG operations and frequency measurement, thereby reducing the need for additional dedicated clock monitoring hardware.
2Measurement precision
If a separate clock monitor circuit is used to test the frequency of generated clock signals, then the frequency testing capability is improved, but the routing complexity increases
Solution Approach 1:
The patent merges the clock monitor functionality into the ATPG circuit by utilizing the existing scan chain and flip-flops. The scan chain is configured to capture clock signal transitions, and the ATPG circuit itself performs frequency measurement by counting clock cycles during the capture phase, eliminating the need for a separate clock monitor circuit and reducing overall circuit area.
3Loss of time
If the ATPG circuit is modified to include frequency testing capability, then the testing process time is reduced, but the circuit complexity increases
Solution Approach 1:
The patent employs periodic action by utilizing the phased operation of the scan chain. During the capture phase, the scan chain captures clock signal transitions into its flip-flops. During the shift-out phase, the captured data representing clock frequency information is shifted out and processed. This periodic capture and measurement approach enables frequency testing to be integrated into the existing ATPG test cycle without requiring continuous monitoring hardware, thereby limiting the increase in circuit complexity.
Data Source
AI summary
Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.