PCIe ATS DMA Attack Detection via IOMMU Validation

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Solution Overview

Problem

The current Address Translation Services (ATS) in PCIe protocol, while enhancing performance by caching address translations, poses a security threat as it can bypass IOMMU memory access protections, potentially allowing unauthorized devices to access memory regions they are not permitted to access.

Innovation Solution

An attack discovery unit device is instantiated in the PCIe root complex to detect ATS-based direct memory access (DMA) attacks by maintaining tables that record valid memory address translations and checking each DMA request against these records to identify unauthorized or malicious access attempts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If ATS is enabled to cache address translations, then system performance is improved, but security protection is weakened

Engineering Contradiction:
Improvesystem performanceVSAvoidsecurity protection
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an IOMMU as an intermediary component between the ATS cache and the memory system. The IOMMU intercepts and validates address translations, ensuring that cached translations in ATS do not bypass security checks. This mediator verifies that translated addresses correspond to authorized memory regions, thus maintaining security while allowing ATS performance benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the IOMMU monitors and validates address translations performed by ATS-enabled devices. When a translation is requested, the IOMMU checks the translated address against authorized regions and provides feedback to the system about whether the translation is secure. This feedback loop ensures that performance-optimized cached translations do not compromise security.

Inventive Principle:
Principle #23Feedback

2Speed

If ATS-enabled devices provide address translations, then access speed is improved, but unauthorized access risk increases

Engineering Contradiction:
Improveaccess speedVSAvoidunauthorized access risk
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary validation of address translations by the IOMMU before the translated addresses are used to access memory. The IOMMU pre-checks whether the translation requests from ATS-enabled devices correspond to authorized memory regions, and only allows translations that pass security validation. This preliminary security check prevents unauthorized access while maintaining fast access speeds for authorized translations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11899593B2Method and apparatus for detecting ATS-based DMA attack
Publication Date: 2024.02.13 INTEL CORP
  • US11899593B2 patent drawing
  • US11899593B2 patent drawing
  • US11899593B2 patent drawing

AI summary

Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a computer-readable memory for storage of data, the computer-readable memory comprising a first memory buffer and a second memory buffer, an attack discovery unit device comprising processing circuitry to perform operations, comprising, receiving a direct memory access (DMA) request from a remote device via a Peripheral Component Interconnect Express (PCIe) link, the direct memory access (DMA) request comprising a host physical address and a header indicating that the target memory address has previously been translated to a host physical address (HPA), and blocking a direct memory access in response to a determination of at least one of that the remote device has not obtained a valid address translation from a translation agent, or that the remote device has not obtained a valid translation for the target memory address from the translation agent.