At-Speed Scan DVFS for SoC Timing Margin Optimization
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Solution Overview
Problem
Existing dynamic voltage frequency scaling (DVFS) techniques often rely on excessive clock margins to avoid timing violations, which can lead to increased latency and power consumption.
Innovation Solution
The implementation of a sensor-based system that uses at-speed scans to determine optimal voltage-frequency operating combinations, ensuring sufficient margins while minimizing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excessive clock margins are used to avoid timing violations, then timing reliability is improved, but latency and power consumption increase
Solution Approach 1:
The patent implements dynamic clock margin adjustment where the clock margin is not fixed but varies based on real-time operating conditions. The system dynamically selects appropriate clock margins from multiple predefined margins and adjusts them during operation to match actual timing requirements, thereby avoiding both timing violations and excessive latency.
Solution Approach 2:
The system changes the clock margin parameter dynamically based on detected operating conditions such as temperature, voltage, and workload. By transitioning between different clock margin values (e.g., from conservative to aggressive margins) depending on the operational state, the system optimizes the balance between timing reliability and performance.
2Reliability
If excessive clock margins are used to avoid timing violations, then timing reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock margin adjustment where the clock margin is not fixed but varies based on real-time operating conditions. The system dynamically selects appropriate clock margins from multiple predefined margins and adjusts them during operation to match actual timing requirements, thereby avoiding both timing violations and excessive latency.
Solution Approach 2:
The system changes the clock margin parameter dynamically based on detected operating conditions such as temperature, voltage, and workload. By transitioning between different clock margin values (e.g., from conservative to aggressive margins) depending on the operational state, the system optimizes the balance between timing reliability and performance.
3Ease of manufacture
If fixed clock margins are used, then implementation simplicity is improved, but adaptability to varying operating conditions deteriorates
Solution Approach 1:
The patent implements dynamic clock margin adjustment where the clock margin is not fixed but varies based on real-time operating conditions. The system dynamically selects appropriate clock margins from multiple predefined margins and adjusts them during operation to match actual timing requirements, thereby avoiding both timing violations and excessive latency.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor operating conditions such as temperature, voltage, and timing performance. Based on this feedback, the system automatically adjusts clock margins to maintain optimal operation. The feedback loop enables the system to adapt to varying conditions while maintaining timing reliability.
Data Source
AI summary
An example method can include performing a first sensing operation associated with circuitry on a system on chip (SoC) to determine a first data value, performing a second sensing operation associated with circuitry of a sensor the SoC to determine a second data value, responsive to the first data value and the second data value being the same data value, determining that a clock margin is sufficient, and responsive to the first data value and the second data value being different data values, determining that a clock margin is insufficient. In some examples, a voltage-frequency operating combination associated with at least one operation of the SoC can be adjusted to a particular stored voltage-frequency operating combination that provides a sufficient clocking margin.