At-Speed Scan Test Pattern Speed-Path Debug

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Solution Overview

Problem

Current speed-path debug techniques for integrated circuits are time-consuming and inefficient, as they rely on functional test patterns and traditional logic fault diagnosis methods that struggle to identify all failing signal propagation paths, especially when multiple paths are involved, and often miss critical speed paths due to inaccuracy and pattern independence.

Innovation Solution

The use of two-cycle at-speed scan test patterns to identify and rank suspect speed paths by tracing signal propagation paths, employing logic simulation and unknown 'X' values to model defects, and applying pruning rules to eliminate non-critical paths, followed by ranking techniques based on structural properties and SDF timing information to prioritize paths for modification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If functional test patterns are used for speed-path debug, then the debug process can identify critical paths, but the process becomes time-consuming and requires extensive design experience and knowledge

Engineering Contradiction:
Improveidentification accuracy of critical pathsVSAvoiddebug time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the test pattern parameters from functional patterns to at-speed scan patterns, which are specifically designed to exercise critical paths at the target operating speed. This parameter change allows automated identification of speed paths without requiring extensive design experience, thus reducing both time loss and maintaining identification accuracy

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the manual, experience-based functional pattern debugging approach with an automated at-speed scan pattern-based system. This substitution eliminates the need for debug engineers to have extensive architectural knowledge and functionality understanding, significantly reducing the time required while maintaining or improving identification accuracy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If traditional SLAT diagnosis concepts are applied to at-speed defects, then single defects can be diagnosed, but multiple failing paths cannot be effectively identified

Engineering Contradiction:
Improvedefect diagnosis resolutionVSAvoidcapability to handle multiple paths
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent extends the diagnosis capability from handling single defects (SLAT concept) to handling multiple simultaneous defects and failing paths. The at-speed scan pattern methodology is designed to exercise multiple critical paths concurrently, and the analysis system is adapted to identify all failing paths in a unified manner, providing both precision and versatility

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the diagnosis process into distinct phases: pattern application, failure detection, path identification, and ranking. This segmentation allows the system to effectively handle multiple failing paths by analyzing each path independently while maintaining the ability to diagnose single defects with high resolution when applicable

Inventive Principle:
Principle #1Segmentation

3Reliability

If the number of suspect speed paths is large, then comprehensive coverage is achieved, but debug efficiency decreases due to the large number of paths to investigate

Engineering Contradiction:
Improvecoverage of critical pathsVSAvoiddebug efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces ranking parameters based on structural properties and SDF timing information to prioritize suspect paths. By changing the selection criteria from exhaustive listing to ranked prioritization, the system maintains comprehensive coverage for reliability while improving debug efficiency by directing attention to the most critical paths first

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a two-phase approach: first identifying all suspect paths to ensure comprehensive coverage, then ranking and prioritizing them to focus debug efforts on the most critical subset. This partial action on the ranked list maintains reliability through complete identification while achieving productivity gains through focused investigation

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8468409B2Speed-path debug using at-speed scan test patterns
Publication Date: 2013.06.18 SIEMENS INDUSTRY SOFTWARE INC
  • US8468409B2 patent drawing
  • US8468409B2 patent drawing
  • US8468409B2 patent drawing

AI summary

Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked.