At-Speed Scan Test Circuitry for Delay Fault Detection
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Solution Overview
Problem
Integrated circuits with high densities face challenges in efficient testing with high failure coverage and low test costs, as existing design for testability (DFT) techniques are complex and costly, particularly in detecting delay faults across clock domains with different frequencies or phases.
Innovation Solution
The integrated circuit employs a method for delay-fault testing using a pulse generator and multiplexer circuits to selectively configure memory cells as scan test memory cells, generating launch and capture test clock pulses at frequencies proportional to the application speed, allowing for efficient detection of delay faults without requiring high-end automated test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DFT techniques are used for testing integrated circuits, then failure coverage can be achieved, but test complexity and cost increase significantly
Solution Approach 1:
The patent combines scan chain functionality with operational memory cells into a unified structure. The same memory cells serve both as operational storage elements and as scan test elements when configured in scan mode, eliminating the need for separate dedicated test memory structures and reducing overall test circuit complexity
Solution Approach 2:
The memory cells are designed with multi-functionality, capable of operating in both operational mode and scan test mode. The circuitry can selectively configure these cells between their normal computational function and their test function, allowing a single structure to fulfill multiple purposes and reducing the need for additional dedicated test components
2Reliability
If existing DFT techniques are used for testing integrated circuits, then failure coverage can be achieved, but test cost increases
Solution Approach 1:
The patent merges operational memory cells with scan test functionality, eliminating the need for separate dedicated test memory structures. This consolidation reduces the overall amount of circuitry required, leading to lower manufacturing costs and reduced test equipment requirements
Solution Approach 2:
The multi-functional memory cells that can operate in both operational and scan test modes reduce the need for additional dedicated test components. This universality decreases the overall circuit area required for testing and reduces the complexity of test equipment needed, thereby lowering test costs
3Reliability
If memory cells are configured as scan test memory cells, then delay faults can be detected, but the circuit must be reconfigured from operational mode
Solution Approach 1:
The patent implements dynamic reconfiguration capability where memory cells can switch between operational mode and scan test mode based on control signals. This dynamic switching is achieved through mode control logic that adjusts the connectivity and timing of the memory cells, allowing flexible transition between functional states without permanent structural changes
Data Source
AI summary
An integrated circuit has a plurality of clock domains and a plurality of memory cells being configurable as operational memory cells or as scan test memory cells for testing the integrated circuit. A pulse generator of the integrated circuit generates pulses for triggering the memory cells when being configured as scan test memory cells, the pulse generator comprising a plurality of pulse outputs. The pulses are provided to the memory cells by multiplexer circuits selecting one of the pulses of the pulse generator and an operational clock.