Attack-Aware Clock Twin for TSN Time Synchronization

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Solution Overview

Problem

Current time-sensitive networking (TSN) systems lack efficient methods to recover from attacks that disrupt time synchronization and traffic scheduling, leading to potential failures and safety risks in critical applications.

Innovation Solution

Implementing an 'attack-aware digital twin' (AADT) of the clock manager that mirrors clock management operations, using a physics-aware model to detect and mitigate malicious time samples, allowing the system to continue normal operations even under attack.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional clock management is used in TSN systems, then the system structure remains simple, but the system becomes vulnerable to attacks that disrupt time synchronization

Engineering Contradiction:
Improvetime synchronization reliabilityVSAvoidclock management structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a digital twin of the clock manager that replicates the functionality of the original clock manager. This digital twin receives the same time information from the network and independently calculates clock control information, creating a redundant copy that can detect and respond to attacks on the primary clock manager.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The digital twin continuously monitors and prepares alternative clock control information in advance before attacks occur. When an attack is detected on the primary clock manager, the pre-prepared alternative information can be immediately activated without delay, enabling rapid response to synchronization disruptions.

Inventive Principle:
Principle #10Preliminary action

2Ease of repair

If no redundancy is implemented for clock management, then the device complexity remains low, but the system cannot recover from attacks

Engineering Contradiction:
Improvesystem recovery capabilityVSAvoidclock management redundancy
Core Design Contradiction:
Ease of repairVSDevice complexity

Solution Approach 1:

The system dynamically changes the operational state of the clock manager based on detected attack conditions. When attacks are detected, the system transitions from using primary clock control information to using alternative clock control information generated by the digital twin, effectively changing the operational parameters to maintain synchronization.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The digital twin continuously generates and holds ready alternative clock control information as a protective measure before attacks occur. This pre-prepared backup information acts as a cushion that prevents system failure when attacks disrupt the primary clock manager, enabling seamless recovery without interruption to time synchronization.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the system switches to alternative clock information during attacks, then time synchronization reliability improves, but detection precision is required to avoid false switching

Engineering Contradiction:
Improvecontinuous time synchronizationVSAvoidattack detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The system continuously compares time information from multiple sources and monitors the consistency of clock control information generated by both the primary clock manager and the digital twin. This feedback mechanism detects anomalies and inconsistencies that indicate attacks, enabling accurate identification of attack conditions while minimizing false positives through continuous verification.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12609942B2Continued time synchronization in the presence of attacks using attack-aware twin
Publication Date: 2026.04.21 INTEL CORP
  • US12609942B2 patent drawing
  • US12609942B2 patent drawing
  • US12609942B2 patent drawing

AI summary

Techniques for an attack-aware digital twin in a time sensitive network are described. A method includes receiving time information for a network by an attack-aware digital twin (AADT), the AADT to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time desynchronization attack in the network, and removing the malicious time sample from the model clock control information to adjust the clock to the network time for the network. Other embodiments are described and claimed.