Attribute-Based Data Transfer for Memory Power Management
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Solution Overview
Problem
Existing data storage systems face challenges with high costs, power consumption, and mechanical reliability issues, particularly in mobile applications, as traditional semiconductor memories and disk drives have limitations in terms of price, power efficiency, and durability.
Innovation Solution
A data storage system utilizing a plurality of memories connected by a common channel, with a control circuit that sequentially transfers data based on attributes such as programming time or bit significance, allowing for efficient data distribution across multiple groups of memories, reducing peak power consumption and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional semiconductor memories (DRAM/SRAM) are used for external storage, then faster access speed is achieved, but power consumption increases and cost per unit capacity becomes high
Solution Approach 1:
The patent divides the memory system into multiple groups (first group and second group) with different power consumption characteristics. By segmenting the memory operations and selectively activating specific groups based on data attributes, the system achieves fast access when needed while reducing overall power consumption during normal operation.
2Reliability
If DRAM refresh operations are performed, then data retention is maintained, but power consumption makes mobile applications difficult
Solution Approach 1:
The patent dynamically switches between different memory groups based on operational requirements. The system can transition from a high-power fast-access mode to a low-power standby mode, adjusting power consumption in real-time while maintaining data retention capabilities through selective group activation rather than continuous refresh of all memory.
3Productivity
If multiple memories share a common channel, then channel utilization improves, but data transfer efficiency may decrease due to waiting for memory readiness
Solution Approach 1:
The patent prepares data for transfer by organizing it into groups with specific attributes beforehand. The control circuit can preemptively switch between memory groups based on data attributes, ensuring that the target memory is ready to receive data before the transfer begins, thereby eliminating waiting time and maintaining high channel utilization.
4Reliability
If data transfer waits for memory ready status, then data integrity is ensured, but transfer speed decreases
Solution Approach 1:
The system performs preliminary organization of data into attribute-based groups and pre-preps the target memory groups for reception. By ensuring memory readiness in advance through group preparation and attribute matching, the system can execute transfers at high speed without compromising data integrity, as the target memory is already in the correct state to receive data immediately.
Data Source
AI summary
Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data.