Audio Bitstream Reordering for Low-Latency DRAM Access

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Solution Overview

Problem

Current audio processing systems face inefficiencies in memory usage due to high memory bandwidth demands and latency issues, particularly in real-time systems with multiple clients, which affect the burst size and access times of DRAM, leading to suboptimal processing and increased costs.

Innovation Solution

The method involves pre-fetching data and reorganizing audio bit streams to optimize memory usage, employing multiple code tables for efficient encoding and decoding, and utilizing prediction techniques to reduce data transmission, along with pipelining and intra-frame prediction to alleviate memory latency and burst size limitations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is requested from memory only when needed in real-time audio systems, then memory access timing is flexible, but data processing latency increases and productivity decreases

Engineering Contradiction:
Improvedata processing latencyVSAvoiddata processing efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent implements pre-fetching of audio data from memory into buffer memory before it is actually needed for processing. This preliminary action allows the data to be ready when the processor needs it, eliminating waiting time and reducing latency while maintaining high processing efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces buffer memory as an intermediary between main memory and the audio processing unit. This intermediary component decouples the timing requirements of memory access from processing requirements, allowing data to be transferred in advance and processed at the optimal moment without latency penalties.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple clients access DRAM resources in real-time systems, then system functionality increases, but memory bandwidth demands increase and memory access delays increase

Engineering Contradiction:
Improvesystem functionalityVSAvoidmemory access delays
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent divides the memory access requirements of multiple clients into separate buffer memory regions. Each client can have its own buffer or dedicated memory space, allowing simultaneous access without contention. This segmentation eliminates the need for clients to wait for each other, reducing memory access delays while maintaining multi-client functionality.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If code tables are stored in external memory, then device complexity and memory space usage decrease, but data access speed decreases and processing latency increases

Engineering Contradiction:
Improvememory architecture complexityVSAvoidcode table access speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent pre-loads code tables from external memory into buffer memory or cache memory before they are needed for decoding operations. This preliminary loading action ensures that when decoding needs to occur, the code tables are already in fast memory, eliminating access delays while maintaining the benefit of storing tables in external memory for long-term retention.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If DRAM burst length is increased to improve bandwidth efficiency, then memory bandwidth efficiency increases, but system complexity and timing constraint management increase

Engineering Contradiction:
Improvememory bandwidth efficiencyVSAvoidtiming constraint management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses buffer memory as an intermediary that can absorb and manage DRAM burst access patterns. The buffer acts as a buffer zone that can handle large burst transfers from DRAM and then supply data to the processor at smaller, more manageable intervals. This intermediation allows the system to take advantage of long DRAM burst lengths for improved bandwidth efficiency while shielding the rest of the system from the complexity of managing such long burst timing constraints.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8706277B2Method and system for memory usage in real-time audio systems
Publication Date: 2014.04.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8706277B2 patent drawing
  • US8706277B2 patent drawing
  • US8706277B2 patent drawing

AI summary

System and method for encoding, transmitting and decoding audio data. Audio bit steam syntax is re-organized to allow system optimizations that work well with memory latency and memory burst operations. Multiple small entropy coding tables are stored in RAM and loaded to on-chip memory as needed. Audio prediction is pipelined in the bitstream syntax. Intra frames, independent of other frames in the bitstream, are included in the bitstream for error recovery and channel change. New algorithms are implemented in legacy syntax by including the new information in the user data space of the audio frame. The new decoder can use projection to determine where the new information is and read ahead in the stream. Audio prediction from the immediately previous frame is restricted. Audio prediction is performed across channels within a single audio frame. A variable re-order function comprises storing channels of data to DRAM in the order they are decoded and reading them out in presentation order.