Audio Interface Output Buffer Tristating for Fast Bus Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bus protocols, such as the Soundwire® protocol, face challenges in meeting timing requirements for tristating output buffers at faster data rates, particularly in double data rate protocols where devices must release the bus within strict nanosecond deadlines, which is difficult due to propagation delays in semiconductor technologies.
Innovation Solution
The implementation of a logic circuit with delay circuits and a tristate circuit that manages the control input of the output buffer, ensuring compliance with timing requirements by providing sufficient delays to tristate the buffer before the next clock edge, thereby allowing other devices to access the bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission rate is increased to improve productivity, then data transmission speed improves, but the timing requirement for tristating the output buffer becomes more difficult to meet due to propagation delays
Solution Approach 1:
The delay circuit is configured to advance the tristating action of the output buffer before the next clock edge occurs. By introducing a controlled delay period, the buffer is tristated in advance, ensuring compliance with timing requirements even at higher data transmission rates where propagation delays become more critical.
2Manufacturing precision
If delay circuit is added to meet timing requirements, then timing precision improves, but device complexity increases
Solution Approach 1:
The delay circuit modifies the time parameter of the control signal by introducing a controlled delay period. This parameter change allows the output buffer to be tristated at the precise moment required by the bus protocol, meeting timing specifications without requiring complex control logic or multiple circuit components.
Data Source
AI summary
An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.