Audio Interface Output Buffer Tristate Timing Circuit
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Solution Overview
Problem
Existing bus protocols, such as the Soundwire® protocol, face challenges in meeting timing requirements for tristating output buffers, particularly at faster data rates, due to propagation delays in semiconductor fabrication technologies.
Innovation Solution
The integration of a delay circuit and a tristate circuit within an integrated circuit (IC) that includes a tristatable output buffer and an input buffer, where the delay circuit provides controlled delays to ensure timely tristation of the output buffer in compliance with the Soundwire® protocol timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to meet faster data rates, then productivity is improved, but the timing requirement for tristating output buffer within 4 nanoseconds becomes difficult to meet due to propagation delays
Solution Approach 1:
The delay circuit is configured to preliminarily delay the data signal by a first delay amount and the buffer output signal by a second delay amount before they are combined to generate the buffer control signal. This preliminary timing adjustment ensures that the output buffer is tristated within the required 4 nanoseconds of the next clock edge, even at faster data rates where propagation delays would otherwise cause timing violations.
2Manufacturing precision
If propagation delays in semiconductor fabrication are reduced to meet timing requirements, then manufacturing precision is improved, but device complexity increases due to the need for delay circuits
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the data input and the output buffer control. This delay circuit includes delay elements configured to delay the data signal and a buffer output signal by specific delay amounts, and logic circuitry that combines these delayed signals to generate the buffer control signal. The intermediary delay circuit provides the necessary timing precision without requiring changes to the fundamental semiconductor fabrication process.
3Loss of time
If the output buffer is tristated quickly to allow bus access by other devices, then loss of time is reduced, but the risk of bus contention increases if timing is not precisely controlled
Solution Approach 1:
The buffer control signal is generated by combining the delayed data signal with the delayed buffer output signal. This feedback mechanism ensures that the output buffer is tristated at the precise moment when the data has been fully transmitted and the bus is ready for another device, thereby reducing bus access time while preventing bus contention through accurate timing synchronization.
Data Source
AI summary
An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.