Dynamic Audio Clock Control for I2S Buffer Overflow and Underflow

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Solution Overview

Problem

Existing audio applications face issues with audio data overflow or underflow due to mismatches between the data volume of audio data and the bit clock signal of the I2S interface, leading to loss of audio data and playback failure.

Innovation Solution

An audio processing apparatus and method that dynamically adjusts the audio clock by monitoring the data volume of audio packets and adjusting the clock signal frequency based on threshold values, preventing overflow or underflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the BCLK signal is fixed, then the audio processing is simple, but audio data overflow or underflow occurs when data volume does not match the bit clock signal

Engineering Contradiction:
Improveaudio data integrityVSAvoidclock adjustment mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic adjustment of the BCLK signal frequency based on the actual data volume in the audio buffer. The system transitions from a fixed clock frequency to a variable one, allowing the clock to speed up or slow down according to data arrival rates, thereby preventing overflow and underflow conditions while maintaining system reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the system continuously monitors the data volume in the audio buffer and adjusts the BCLK frequency accordingly. When the buffer approaches overflow or underflow thresholds, the system generates interrupt signals that trigger clock frequency adjustments, creating a closed-loop control system that maintains audio data integrity.

Inventive Principle:
Principle #23Feedback

2Reliability

If the clock frequency is dynamically adjusted, then audio data overflow and underflow are prevented, but the system complexity increases

Engineering Contradiction:
Improveaudio data integrityVSAvoidbuffer monitoring and clock control system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-regulating system where the audio processing apparatus automatically monitors its own buffer status and adjusts its clock frequency without external intervention. The buffer monitoring module detects overflow/underflow conditions and triggers interrupt signals that automatically adjust the BCLK frequency, allowing the system to self-correct and maintain optimal operation.

Inventive Principle:
Principle #25Self-service

3Productivity

If the BCLK signal frequency is decreased, then the risk of overflow decreases, but data processing speed reduces

Engineering Contradiction:
Improveaudio data processing speedVSAvoidaudio data integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent dynamically changes the frequency parameter of the BCLK signal based on real-time buffer status. Instead of using a fixed frequency, the system adjusts the clock frequency parameter up or down according to data volume conditions, optimizing both processing speed and reliability by matching the clock rate to the actual data flow characteristics.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12271653B2Audio processing apparatus and audio processing method for dynamically adjusting audio clock
Publication Date: 2025.04.08 REALTEK SEMICON CORP
  • US12271653B2 patent drawing
  • US12271653B2 patent drawing
  • US12271653B2 patent drawing

AI summary

An audio processing apparatus and an audio processing method for dynamically adjusting an audio clock are provided. The audio processing apparatus includes a first interface, a buffer, a clock generator, a processor, and a second interface. The first interface receives audio data from the host. The buffer stores the audio data to generate a first audio packet and determines relationships between a data volume of the first audio packet and a first upper threshold and a first lower threshold. The second interface outputs the first audio packet and a clock signal to a codec apparatus. In response to the data volume of the first audio packet being less than the first lower threshold, the buffer outputs an underflow interrupt signal. In response to the data volume of the first audio packet being greater than the first upper threshold, the buffer outputs an overflow interrupt signal.