Digital PLL Frequency Generation for Low-Jitter Audio Clocks
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Solution Overview
Problem
Digital PLLs are undesirable for audio codec applications due to clock jitter, which limits dynamic performance and sound quality, while analog PLLs are resource-intensive and costly, making them unsuitable for shrinking audio playback devices.
Innovation Solution
A digital phase locked loop circuit with a digital numerical controlled oscillator and extra pulse eliminator, capable of generating a target frequency from a system clock with minimal jitter, allowing flexible operation at any data rate and clock frequency, reducing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a digital PLL is used to generate clock signals, then resource consumption and cost are reduced, but clock jitter increases which degrades dynamic performance and sound quality
Solution Approach 1:
The patent replaces the traditional analog PLL (mechanical/electrical continuous system) with a digital PLL using a digital numerical controlled oscillator. This substitution reduces resource consumption and cost while managing clock jitter through digital control mechanisms including a multi-bit integrator and extra pulse eliminator that process clock signals in discrete time domains.
Solution Approach 2:
The patent changes the operational parameters of the clock generation system by using a multi-bit integrator with adjustable numerical inputs and an extra pulse eliminator that selectively removes pulses. These parameter changes allow the digital PLL to generate accurate target frequencies from system clocks with different frequencies, reducing clock jitter while maintaining low power consumption.
2Reliability
If an analog PLL is used to generate clock signals, then clock jitter is minimized improving sound quality, but resource consumption and device complexity increase
Solution Approach 1:
The patent extracts the critical jitter-reduction functions from the complex analog PLL structure and implements them separately in the digital domain using a multi-bit integrator and extra pulse eliminator. This extraction maintains sound quality by addressing clock jitter while significantly reducing overall circuit complexity and resource requirements.
Solution Approach 2:
The patent introduces a multi-bit integrator as an intermediary component between the system clock and the numerical controlled oscillator. This intermediary processes the clock signals digitally, enabling accurate frequency generation with minimal jitter while keeping the overall system simpler than traditional analog PLLs.
3Reliability
If the system clock frequency is changed to match audio data rate, then clock synchronization is improved, but adaptability to different audio formats is reduced
Solution Approach 1:
The patent implements a dynamic numerical controlled oscillator that can adjust its output frequency based on the system clock frequency and desired audio data rate. This dynamic adjustment capability allows the digital PLL to maintain clock synchronization for different audio formats (32, 96, 128, 160, 192, 224, 320 Kbits/s) without requiring the system clock to match each specific data rate.
Solution Approach 2:
The patent creates a universal clock generation system using a digital PLL that can handle multiple audio data rates and system clock frequencies. The multi-bit integrator and extra pulse eliminator work together to provide this multi-functionality, allowing the same circuit to support various audio formats and master clock rates without sacrificing synchronization quality.
Data Source
AI summary
Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency are disclosed. In one aspect of the present disclosure, the circuit includes, a digital phase locked loop coupled to the system clock. The digital phase locked loop including an oscillator output and an oscillator input. The circuit further comprises an extra pulse eliminator coupled to the oscillator output. The extra pulse eliminator includes an extra pulse eliminator output. One or more frequency dividers may be coupled to an extra pulse eliminator output.