Dual-Clock Frequency Locking for Low-Jitter Audio Clock Generation
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Solution Overview
Problem
Existing frequency locked loops (FLLs) in digital audio signal processing face challenges in generating a high-quality clock signal with low jitter, especially when the input clock is of poor quality or experiences degradation, leading to noise, distortion, and spurious tones, and require minimal external components for integrated circuit implementation.
Innovation Solution
A clock generator using a frequency locked loop with two input clock signals and digital filters to produce an output clock signal with low jitter, where one clock signal has higher frequency accuracy and lower jitter, and the other has lower frequency accuracy but higher quality, allowing the output clock to be synchronized with the input data while minimizing external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a frequency locked loop uses a single input clock signal to generate an output clock, then the circuit complexity is reduced, but the output clock quality (jitter performance) deteriorates when the input clock is of poor quality
Solution Approach 1:
The patent divides the clock generation system into two separate input paths: one path receives a first clock signal (e.g., from a crystal oscillator) and another path receives a second clock signal (e.g., from a PLL). Each path processes its respective clock signal independently through separate frequency comparators and digital filters, allowing the system to combine the advantages of both clock sources without increasing overall circuit complexity significantly.
Solution Approach 2:
The patent introduces a digital filter as an intermediary component that processes the error signal from the frequency comparator. This digital filter acts as a mediator between the frequency comparison stage and the numerically controlled oscillator, enabling the system to achieve low jitter performance by filtering out high-frequency noise and spurious signals while maintaining the beneficial properties of both input clock sources.
2Productivity
If the output clock frequency is multiplied from the input clock frequency to achieve higher frequency operation, then the productivity increases, but the jitter and noise in the output clock worsen
Solution Approach 1:
The patent implements a feedback mechanism where the output clock signal is fed back to a frequency comparator that compares its frequency against the input clock signal. The difference (error signal) is processed through a digital filter and used to adjust the numerically controlled oscillator, creating a closed-loop system that automatically corrects frequency deviations and reduces jitter even at multiplied output frequencies.
Solution Approach 2:
The patent replaces traditional analog phase-locked loop mechanisms with a numerically controlled oscillator and digital filtering system. This substitution allows for precise digital control of the output frequency while effectively filtering out jitter and noise through digital signal processing, enabling high-frequency operation with improved jitter performance compared to conventional analog approaches.
3Reliability
If digital filtering is applied to reduce jitter and noise in the output clock, then the output clock quality improves, but the device complexity increases
Solution Approach 1:
The patent replaces complex analog filtering circuits with digital filters implemented in the frequency locked loop. This substitution achieves effective jitter and noise reduction through digital signal processing while maintaining relatively simple circuit architecture, as the digital filter can be implemented using standard digital logic components rather than requiring complex analog filter designs.
4Ease of manufacture
If the clock generator is designed for integrated circuit implementation with minimal external components, then the ease of manufacture improves, but the ability to achieve low jitter without external components such as large capacitors worsens
Solution Approach 1:
The patent replaces the need for external analog components (such as large capacitors and complex analog filter circuits) with digital filtering implemented entirely within the integrated circuit. The digital filter processes the error signal in the digital domain, achieving effective jitter reduction without requiring external passive components, thus enabling compact integrated circuit implementation while maintaining high output clock quality.
Data Source
AI summary
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.