Audio Clock Synchronization via Network Time Correlation

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Solution Overview

Problem

Networked audio devices often experience synchronization issues due to differing clock signals, particularly between the computing device's D/A converter and network interfaces, leading to time offsets and drift, which affect the synchronization of audio speakers connected via wires or wireless LANs.

Innovation Solution

Implementing a synchronization routine that reads and correlates counters representing the time of the network and audio device clocks, using IEEE standard 802.1AS, to adjust the audio clock and ensure synchronization across all connected speakers, both physically and wirelessly, through sample rate conversion and clock adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple independent clock sources are used for network interfaces and audio devices, then device functionality and independence are improved, but clock synchronization and timing accuracy deteriorate

Engineering Contradiction:
Improvedevice functionalityVSAvoidclock synchronization
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces a master clock as an intermediary reference that both network interfaces and audio devices use to synchronize their operations. This master clock acts as a mediator that coordinates timing across all components, allowing them to maintain independent functionality while achieving synchronized operation through the common reference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback mechanisms where clock counters are continuously monitored and compared across different devices. The synchronization routine reads counters from multiple sources, calculates time offsets, and adjusts timing parameters based on the measured deviations, creating a closed-loop control system that maintains synchronization.

Inventive Principle:
Principle #23Feedback

2Device complexity

If separate clock signals are used for network and audio hardware, then hardware independence is improved, but time offset and drift increase

Engineering Contradiction:
Improvehardware independenceVSAvoidtime offset stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent employs dynamic sample rate conversion that can adjust in real-time based on measured clock drift and time offsets. The system continuously monitors the relationship between network and audio clocks and dynamically modifies sampling parameters to compensate for frequency differences, maintaining synchronization despite hardware independence.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The synchronization system changes operational parameters such as sample rates, buffer sizes, and timing intervals based on the measured state of clock synchronization. When drift or time offsets are detected, the system adjusts these parameters to realign the timing between network and audio subsystems.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If real-time clock correlation is implemented across multiple devices, then synchronization accuracy is improved, but system complexity increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the synchronization system into separate functional modules: a master clock generation unit, individual device clock units, a counter reading and correlation module, and a parameter adjustment module. Each module performs a specific function, making the overall complex system manageable through functional segmentation and independent optimization of each component.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8934505B2Synchronizing multiple system clocks
Publication Date: 2015.01.13 INTEL CORP
  • US8934505B2 patent drawing
  • US8934505B2 patent drawing
  • US8934505B2 patent drawing

AI summary

Techniques are disclosed for synchronizing multiple clock sources of a system, and may include: determining time of a first clock at a first and second time instants; determining time of a second clock at a third time instant occurring between the first and second time instants, and a fourth time instant occurring after the second time instant; and determining a clock offset between the first and second clocks based on the determined times. The first and/or second clocks may be adjusted based on the clock offset to synchronize clock operation. This adjusting can be used, for instance, to synchronize operation of an audio and/or video component operating according to the first clock with an audio and/or video component operating according to the second clock. The techniques may further include determining if the clock offset is valid (e.g., based on detection of perturbing events or difference between a clock's times).