Software Audio Clock Synchronization via Estimator SRC
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Solution Overview
Problem
Existing wireless network technologies fail to accurately synchronize sample clocks across multiple network endpoints, leading to channel-to-channel latency and packet loss issues that affect the quality of multi-channel audio and video streaming.
Innovation Solution
The implementation of an Estimator and a Sample Rate Converter (SRC) code replaces hardware PLL functions, introducing a frequency filtering function to recover and synchronize band-limited sample clocks, ensuring consistent timing across network endpoints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware PLL is used to filter TSF value and generate audio clock, then synchronization accuracy is improved, but device complexity increases due to specialized hardware requirements
Solution Approach 1:
The patent replaces the hardware PLL (Phase-Locked Loop) circuit with software implementations including an Estimator module and Sample Rate Converter (SRC) code. The Estimator software module filters the TSF (Time Synchronization Function) value and the SRC generates the audio clock signal, achieving the same synchronization function without requiring specialized hardware PLL circuits. This substitution resolves the contradiction by maintaining synchronization accuracy while reducing hardware complexity.
Solution Approach 2:
The patent implements a universal software-based timing system that can operate on generic processor SOCs without requiring specialized hardware. The Estimator and SRC code provide multi-functional capabilities including TSF filtering, audio clock generation, and sample rate conversion within a single software framework, eliminating the need for separate dedicated hardware components and reducing overall device complexity.
2Ease of manufacture
If wireless network transmission is used for audio/video data, then ease of installation is improved, but synchronization accuracy deteriorates due to packet loss and latency
Solution Approach 1:
The patent implements feedback mechanisms where the Estimator continuously monitors the relationship between wall clock time and TSF values, adjusting its filtering parameters in real-time. The system uses feedback from packet arrival times and timestamps to compensate for wireless transmission variations, maintaining synchronization accuracy despite the inherent instability of wireless networks. This feedback approach allows the system to adapt to packet loss and latency variations.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing timing adjustment parameters based on historical synchronization data. The Estimator module prepares filtered TSF values and timing corrections in advance, allowing the system to compensate for anticipated packet loss and latency variations before they affect synchronization accuracy. This preliminary processing helps maintain timing accuracy despite wireless transmission imperfections.
3Device complexity
If software-based Estimator and SRC code is used instead of hardware PLL, then device complexity is reduced, but processing time increases
Solution Approach 1:
The patent applies partial action by implementing optimized software algorithms that perform only the necessary computational steps for timing synchronization. The Estimator module uses selective filtering techniques that process only the critical timing components rather than all possible signal parameters, reducing processing time while maintaining synchronization accuracy. The SRC code uses efficient resampling algorithms that achieve the required sample rate conversion with minimal computational overhead.
Solution Approach 2:
The patent changes processing parameters dynamically based on system conditions. The Estimator adjusts its filtering parameters and the SRC modifies its resampling rates according to current network conditions and processing requirements. By adapting these parameters in real-time, the system optimizes processing speed while maintaining synchronization accuracy, reducing the time penalty associated with software-based implementation.
Data Source
AI summary
Synchronization of plural outputs of data transported by a wireless network is facilitated by bandlimiting a sample clock signal controlling a rate at which data is processed by the network's devices and/or bandlimiting wall time data controlling the real time for presenting a datum.