Software Audio Clock Synchronization via Estimator and SRC

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Solution Overview

Problem

Existing wireless network technologies fail to accurately synchronize sample clocks across multiple network endpoints, leading to channel-to-channel latency and packet loss issues that affect the quality of multi-channel audio and video streaming.

Innovation Solution

The implementation of an Estimator and a Sample Rate Converter (SRC) code replaces hardware PLL functions, enabling frequency filtering and synchronization of sample clocks, which are then bandlimited to reduce jitter and ensure consistent timing across network endpoints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If hardware PLL is used to filter TSF value and generate audio clock, then synchronization precision is improved, but device complexity increases

Engineering Contradiction:
Improvesynchronization precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces the hardware PLL (Phase Locked Loop) circuit with software-based Estimator and Sample Rate Converter code implementations. This substitution eliminates the need for specialized hardware components while achieving the same frequency filtering and synchronization functions through software algorithms running on general-purpose processors.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements multi-functional capabilities using software components. The Estimator and Sample Rate Converter code perform multiple functions including frequency filtering, timing adjustment, and clock generation that previously required separate hardware PLL blocks, thereby reducing hardware complexity while maintaining functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If wireless network transmission is used for audio/video data, then ease of operation is improved, but synchronization precision deteriorates

Engineering Contradiction:
Improveease of operationVSAvoidsynchronization precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms where the Estimator continuously monitors timing differences between network packets and local clock, adjusting synchronization parameters in real-time. This feedback loop compensates for wireless network variations and maintains precise synchronization despite the inherent imprecision of wireless transmission.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary timing adjustments and frequency filtering before actual audio/video playback. By pre-processing the timing information through the Estimator and Sample Rate Converter, the system prepares synchronized timing data in advance, ensuring that even though wireless transmission is imprecise, the final output maintains synchronization precision.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If software-based Estimator and SRC code replaces hardware PLL, then device complexity is reduced, but manufacturing precision deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoidmanufacturing precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent adjusts software parameters such as filter coefficients, sampling rates, and timing offsets to achieve precise synchronization. By optimizing these software parameters, the system compensates for the lack of hardware precision, maintaining manufacturing precision through algorithmic adjustment rather than hardware accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10602468B2Software based audio timing and synchronization
Publication Date: 2020.03.24 DATAVAULT AI INC
  • US10602468B2 patent drawing
  • US10602468B2 patent drawing
  • US10602468B2 patent drawing

AI summary

Synchronization of plural outputs of data transported by a wireless network is facilitated by band limiting a sample clock signal controlling a rate at which data is processed by the network's devices and/or band limiting wall time data controlling the real time for presenting a datum.