Audio Codec Control Sequencer for Precise Register Write Timing
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Solution Overview
Problem
Existing audio codecs face challenges in ensuring precise delays between commands for register writes, leading to potential operational issues such as pops and clicks in analogue outputs, and increased latency due to combined control and data interfaces, which complicates the configuration and operation of audio systems.
Innovation Solution
A control sequencer is introduced between the control interface logic and control registers, enabling precise timing of register writes through a state machine and memory for storing sequences, with a multiplexer for selective coupling, allowing preloading and execution of command bursts with defined delays, independent of external processor direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a combined serial interface is used for control and data to reduce pin count, then device packaging is simplified, but latency between commands increases
Solution Approach 1:
The patent segments the control interface into two separate interfaces: a control interface for sending commands and a data interface for transferring audio data. This segmentation allows simultaneous operation of control and data transfers, eliminating the latency caused by time-multiplexed combined interfaces while maintaining reduced pin count through efficient interface design.
2Reliability
If the control processor manages all control operations directly, then precise timing can be maintained, but the processor load increases
Solution Approach 1:
The patent introduces a control sequencer as an intermediary component between the control processor and the audio codec. The sequencer receives timing parameters from the processor, stores them in a timing register, and automatically generates precisely timed control signals. This allows the processor to set timing parameters once and then handle other tasks, maintaining timing precision while reducing processor load.
Solution Approach 2:
The control sequencer pre-loads timing parameters and control sequences into memory before execution is needed. The timing register is pre-configured with delay values, and the sequencer is pre-programmed with the required control sequence. This preliminary preparation enables automatic execution with precise timing without requiring continuous processor intervention.
3Speed
If register writes are executed immediately upon receiving commands, then responsiveness is improved, but precise delay control becomes difficult
Solution Approach 1:
The patent implements a feedback mechanism where the control sequencer continuously monitors the timing register and automatically adjusts the execution timing of register writes. The sequencer reads the current time, compares it with the predetermined timing parameters, and executes writes only when the timing conditions are met. This feedback loop ensures precise delay control while maintaining responsive execution.
Data Source
AI summary
An audio codec (100) is provided with a control sequencer (110) interposed between control interface logic (120) and control registers (130) of the codec. A memory (114, 116) associated with the control sequencer (110) enables a burst of operations to be preloaded into the audio codec. In response to a single command from an external control processor (20), the sequencer (110) can then execute the burst with precise delays between each operation and without further direction from the processor. This frees the processor (20) to concentrate on other tasks within the system, and/or to enter a low-power mode to conserve energy. The system may be a personal media player.