Multi-Core Audio Deadline Scheduling for Low-Latency Streams
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Solution Overview
Problem
Existing solutions for scheduling audio processing tasks in real-time systems fail to satisfactorily meet performance criteria such as latency and power consumption, particularly in multi-core audio processors handling multiple streams of data.
Innovation Solution
A multi-core audio processor with a deadline scheduler that maintains a priority list for processing tasks, dynamically updates processing orders based on deadline values and status indications from transport buffers, and outputs vectors to audio processing cores to ensure efficient task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scheduling methods are used for audio processing tasks, then device complexity is reduced, but latency and power consumption performance deteriorate
Solution Approach 1:
The scheduling system is segmented into multiple independent components: deadline registers for each stream, status indication logic for transport buffers, priority list maintenance structures, and per-core vector output mechanisms. This segmentation allows each component to operate independently and efficiently, improving latency performance without creating a monolithic complex scheduler.
Solution Approach 2:
Deadline values are pre-calculated and stored in deadline registers for each stream before processing occurs. The system performs preliminary actions by maintaining ready-computed deadlines and status indications, allowing audio processing tasks to be scheduled and executed immediately when resources are available, thereby reducing latency without requiring complex real-time calculations during processing.
2Reliability
If traditional scheduling methods are used for audio processing tasks, then device complexity is reduced, but power consumption performance deteriorates
Solution Approach 1:
The scheduling system is self-service in that deadline registers automatically maintain deadline values, transport buffers self-generate status indications when full or empty, and the priority list is automatically updated based on these status indications. This self-service mechanism eliminates the need for complex centralized control logic, reducing power consumption while maintaining reliable scheduling performance.
Solution Approach 2:
The system uses periodic deadline values and status indication checks to trigger scheduling decisions. Rather than continuous monitoring and complex decision-making, the scheduler operates on periodic events (deadline expirations, buffer status changes), which reduces computational overhead and power consumption while maintaining effective task scheduling.
3Productivity
If dynamic priority updates are implemented based on deadline values, then productivity is improved, but device complexity increases
Solution Approach 1:
Each stream is assigned its own deadline register with locally maintained deadline values and priority information. The priority list is organized by processing core, with each core having its own vector output and task queue. This local quality approach allows dynamic priority updates to occur in distributed, independent locations rather than requiring centralized complex coordination, thereby improving audio stream processing efficiency without proportionally increasing overall system complexity.
Data Source
AI summary
A multi-core audio processor includes a plurality of audio processing cores having differing capabilities, a plurality of buffers, wherein each buffer is configured to store a plurality of samples associated with a corresponding audio stream, a deadline scheduler including a plurality of deadline registers configured to store a plurality of deadline values for each audio stream, and a plurality of audio processing core interfaces coupling the plurality of audio processing cores to the deadline scheduler, each of the audio processing core interfaces associated with a corresponding audio processing core. The plurality of deadline values indicate an order of processing of samples stored in the plurality of buffers by the plurality of processing cores.