Audio Signal Decoding With Dynamic Clock Sync for Card Readers

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Solution Overview

Problem

Portable electronic devices, such as smartphones, are not compatible with Manchester encoded data signals due to audio interface optimizations for voice communication, leading to signal distortion and failure in data decoding.

Innovation Solution

A method for dynamically decoding audio streams by adjusting the encoder and decoder clock frequencies, preprocessing signals to smooth noise, and identifying known start sequences to interpret data blocks, allowing for successful data interpretation without device adaptations, and enabling compatibility with various devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If audio interface optimizations for voice communication are applied, then sound quality is improved, but data signal interpretation fails

Engineering Contradiction:
Improvesound qualityVSAvoiddata decoding success
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent introduces an intermediary preprocessing step between the audio interface and decoder. This preprocessing stage includes smoothing the received signal and detecting zero-crossing points to identify the actual clock frequency, thereby mediating between the optimized audio interface output and the data decoding requirement. This intermediary processing converts the distorted signal into a form that can be successfully decoded.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically adjusts the clock frequency parameter based on detected zero-crossing points in the signal. Instead of using a fixed clock frequency, the system measures the actual frequency from the distorted signal and adapts the decoding process accordingly. This parameter change allows the decoder to synchronize with the actual signal frequency despite audio interface distortions.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If fixed clock frequency decoding is used, then decoder simplicity is maintained, but compatibility with different devices is lost

Engineering Contradiction:
Improvedecoder complexityVSAvoiddevice compatibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent transforms the static fixed clock frequency approach into a dynamic system that automatically adapts to different devices. The decoder measures the actual clock frequency from the received signal by detecting zero-crossing points and adjusts its operation accordingly. This dynamic adaptation enables compatibility with multiple device types without requiring complex device-specific configuration or multiple decoder variants.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If signal preprocessing is added, then decoding accuracy is improved, but processing time increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies a targeted preprocessing approach rather than comprehensive signal processing. Specifically, it focuses on smoothing the signal and detecting zero-crossing points to determine clock frequency, rather than applying full-spectrum analysis or complex filtering. This partial action provides sufficient decoding accuracy while minimizing additional processing time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9805730B2Dynamic decoding of communication between card reader and portable device
Publication Date: 2017.10.31 PAYPAL INC
  • US9805730B2 patent drawing
  • US9805730B2 patent drawing
  • US9805730B2 patent drawing

AI summary

The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises pre-processing the received encoded data signal; scanning the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating an actual frequency based on the detected start sequence; interpreting, a data block succeeding the start sequence using the assessed actual frequency; and assessing whether to request adjustment of the adjustable encoder clock frequency based on the scanning and/or the interpretation. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.