Audio FIFO Clock Control for Continuous HDMI Reception

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Solution Overview

Problem

In HDMI data transmission systems, the mismatch between data storage and read rates in FIFO memory can lead to overflow or underflow, causing discontinuous audio regeneration and degrading audio quality, especially when transmission errors or faults occur.

Innovation Solution

A receiving system that extracts a clock parameter from the transmission signal, adjusts it based on the data storage rate, and sets the read frequency to maintain a stable data storage rate within predetermined limits, preventing FIFO memory overflow or underflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the read frequency is fixed based on the transmitted clock parameter, then the audio data can be read in synchronization with the transmission system, but the data storage rate of the FIFO memory fluctuates causing overflow or underflow

Engineering Contradiction:
Improveaudio data continuityVSAvoidFIFO memory stability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies dynamics by making the read frequency adjustable rather than fixed. The receiving system dynamically changes the read frequency based on the actual data storage rate of the FIFO memory, allowing the system to adapt to fluctuations in data storage and maintain stable operation without overflow or underflow.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by monitoring the data storage rate of the FIFO memory and using this information to adjust the read frequency. The receiving system continuously compares the actual data storage rate with the expected rate and modifies the read frequency accordingly to maintain proper synchronization and prevent memory overflow or underflow.

Inventive Principle:
Principle #23Feedback

2Productivity

If the read frequency is increased to match higher storage rate, then overflow is prevented, but underflow occurs when storage rate decreases

Engineering Contradiction:
Improvedata read rateVSAvoidaudio data continuity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts the read frequency based on real-time monitoring of the data storage rate. When the storage rate increases, the read frequency is increased to prevent overflow; when the storage rate decreases, the read frequency is reduced to prevent underflow, ensuring continuous reliable audio data regeneration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The receiving system uses feedback from the data storage rate monitoring to continuously adjust the read frequency. This closed-loop control ensures that the read operation matches the storage operation, preventing both overflow and underflow conditions that would disrupt audio continuity.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If the clock parameter is changed to adjust read frequency, then FIFO memory stability is improved, but audio synchronization with transmission system may be affected

Engineering Contradiction:
ImproveFIFO memory stabilityVSAvoidaudio clock synchronization
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent applies parameter changes by modifying the clock parameter used to generate the read frequency. The receiving system adjusts this parameter within a controlled range to maintain FIFO memory stability while ensuring that the audio data remains properly synchronized with the transmission system.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7899133B2Receiving system
Publication Date: 2011.03.01 KK TOSHIBA
  • US7899133B2 patent drawing
  • US7899133B2 patent drawing
  • US7899133B2 patent drawing

AI summary

A receiving system includes: FIFO memory 13 storing audio data AD contained in a transmission signal T; an extraction unit 14 configured to extract a clock parameter contained in the transmission signal T; a parameter change unit 152 configured to change the clock parameter in accordance with a result of a comparison between a data storage rate SR of the FIFO memory 13 and a predetermined value; a frequency setting unit 153 configured to set a read frequency fr using the changed clock parameter; and a data read unit 16 configured to read the audio data AD from the FIFO memory 13 in synchronization with a reception end audio clock signal AC of the read frequency fr.