Digital Audio Mixing Cache Contiguity

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Solution Overview

Problem

In digital audio mixing consoles, the speed of access to the last level cache in CPUs is limited, leading to inefficiencies in combining multiple digital audio signals, especially in systems with a large number of channels, due to memory controller limitations and fragmentation of data in the cache hierarchy.

Innovation Solution

Storing sample values of input digital audio signals in a shared last level cache and writing them to a contiguous portion to reduce cache churn and optimize memory access, allowing for faster retrieval and processing by minimizing memory sharing and maximizing cache locality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a large number of mixing buses are used to handle many input channels, then the number of input signals that can be processed increases, but the number of multiply and addition operations becomes overwhelming for the CPU due to memory access limitations

Engineering Contradiction:
Improvenumber of input channelsVSAvoidCPU processing capacity
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the mixing bus processing into multiple segments by implementing a segmented processing architecture where inputs are divided into groups that can be processed in parallel. This segmentation reduces the computational burden on any single CPU core while maintaining the ability to handle a large total number of inputs through coordinated processing across multiple segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-organizing input data into an optimized data structure before processing begins. Inputs are pre-grouped and arranged in a format that minimizes memory access patterns and optimizes cache utilization during the actual mixing operations, reducing the computational overhead during runtime processing.

Inventive Principle:
Principle #10Preliminary action

2Speed

If data is stored in the last level cache for processing, then processing speed improves, but cache churn increases when data is frequently written and read

Engineering Contradiction:
Improvedata access speedVSAvoidcache churn latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent pre-positions data in the last level cache in an optimized arrangement before processing occurs. By organizing data spatially and temporally in advance, the system minimizes cache evictions and re-loads during processing, reducing cache churn while maintaining fast access speeds throughout the mixing operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transforms the data storage and access pattern by organizing data in a multi-dimensional structure that optimizes for both speed and cache efficiency. This dimensional reorganization allows data to be accessed in patterns that maximize cache hit rates while minimizing evictions, effectively resolving the contradiction between access speed and cache churn.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10038510B2Mixing digital audio
Publication Date: 2018.07.31 SOLID STATE LOGIC UK LTD
  • US10038510B2 patent drawing
  • US10038510B2 patent drawing
  • US10038510B2 patent drawing

AI summary

A method of mixing digital audio uses a plurality of mixing buses. Each mixing bus receives at least one input digital audio signal via a respective input. A sample value (801-805) of each input digital audio signal is stored in shared last level cache in the CPU. Then, for each unique input to the mixing buses in turn, the sample values (801-805) of the input digital audio signals are written (806) to a contiguous portion (808) of the shared last level cache. Then, for each input of each of the mixing buses in turn, the sample value for the corresponding input digital audio signal is added to an output value for the bus (809). When complete, the respective output values (810) for each of the mixing buses is then written to shared last level cache.