Audio Sample Rate Conversion Without PLL Clock Recovery

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Solution Overview

Problem

Conventional audio synchronization methods in video systems require separate audio clocks and phase locked loops (PLLs), increasing system costs and complexity.

Innovation Solution

An audio receiver system that synchronizes audio signals with a reference clock from another device or system, eliminating the need for a separate audio clock and PLL by determining the input number of clocks per frame and re-sampling the audio signal based on this reference, using a conversion module to match the sample rate with the video signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional synchronization approaches use a separate audio clock locked to video clock via PLL, then audio and video signals can be synchronized, but system cost increases

Engineering Contradiction:
Improveaudio-video synchronizationVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the separate audio clock and PLL components from the synchronization system. Instead of using a dedicated audio clock locked to video clock via PLL, the invention uses the existing video clock directly to control audio sample timing, removing the unnecessary intermediate components while maintaining synchronization reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The video clock is made multi-functional by using it for both video signal timing and audio sample timing. The single video clock serves dual purposes: synchronizing video frames and controlling audio sample rate, eliminating the need for separate audio clocking infrastructure and reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple PLLs are used to recover audio clock and lock output audio clock, then audio synchronization is achieved, but device complexity increases

Engineering Contradiction:
Improveaudio clock synchronizationVSAvoidnumber of PLLs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the entire PLL-based audio clock recovery and locking mechanism. By using the video clock directly to timestamp audio samples and control playback rate, the invention eliminates the need for audio clock recovery PLL and output audio clock locking PLL, reducing the system from multiple PLLs to a single shared video clock

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the audio clocking function into the video clocking system. Instead of maintaining separate audio and video clocking paths with multiple PLLs, the invention combines both functions under a single video clock, using it to generate timestamps for audio samples and control audio playback timing, thereby eliminating redundant synchronization hardware

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2815532B1Audio receiver and sample rate converter without PLL or clock recovery
Publication Date: 2019.08.07 INTEL CORP
  • EP2815532B1 patent drawingFigure 1~2
  • EP2815532B1 patent drawingFigure 3A~3B
  • EP2815532B1 patent drawingFigure 4

AI summary

Methods and systems of operating an audio receiver may include a reference module configured to determine an input number of clocks per number of frames for an audio signal based on a reference clock and a specified number of frames. The audio receiver can also include a conversion module configured to re-sample the audio signal based on the input number of clocks per number of frames, the specified number of frames, and a specified number of clocks per number of frames.