Augmented Bus Numbering for Thunderbolt PCIe Networks
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Solution Overview
Problem
PCIe-based architectures face limitations in dynamically reconfiguring network topologies during operation, such as hot-swapping and hot-plugging, due to fixed bus numbering schemes that restrict the expansion of Thunderbolt networks and lead to inefficient resource management.
Innovation Solution
The introduction of Augmented Bus Numbering (ABN) methods and apparatus that dynamically assign and manage bus numbers, allowing for a larger pool of routing resources by creating a three-tier bus numbering system within the Thunderbolt PCIe network, enabling the expansion of supported devices and flexible network reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed bus numbering scheme is used in PCIe-based architectures, then software compatibility with legacy PCI systems is maintained, but the network topology cannot be dynamically reconfigured and the number of supported endpoints is limited
Solution Approach 1:
The bus numbering system is segmented into multiple levels: traditional PCIe bus numbers (0-255) and new routing resources (bridge identifiers, port numbers). This segmentation allows the system to maintain legacy PCIe compatibility while adding dynamic reconfiguration capabilities through additional routing dimensions without increasing single-level complexity
Solution Approach 2:
The patent implements a nested routing structure where traditional PCIe bus numbers are nested within a larger augmented routing space. The bridge device encapsulates multiple subordinate buses, each with its own routing resources, creating a nested hierarchy that expands capacity while maintaining compatibility with existing PCIe addressing schemes
2Quantity of substance
If the number of routing resources is increased to support more endpoints, then the network capacity is expanded, but the resource management complexity increases
Solution Approach 1:
The bridge device serves as an intermediary that manages the expansion of routing resources. It introduces new routing resources (subordinate bus identifiers, port numbers) while maintaining the traditional PCIe bus numbering scheme for compatibility. The bridge handles the complexity of managing multiple routing dimensions, shielding upper-layer software from resource management complexity
Solution Approach 2:
The patent adds another dimension to the routing space by introducing bridge identifiers and port numbers alongside traditional bus numbers. This dimensional expansion allows the system to support more endpoints without linearly increasing the complexity of single-dimension resource management, as routing now occurs across multiple independent dimensions
3Ease of operation
If traditional PCIe bus numbers are used, then compatibility with legacy PCI software architecture is maintained, but hot-swapping and hot-plugging operations are restricted
Solution Approach 1:
The patent introduces dynamic routing resource allocation where bridge devices can allocate and deallocate subordinate bus identifiers and port numbers based on real-time connectivity status. This dynamic allocation enables hot-swapping and hot-plugging operations by allowing the routing table to be updated without system shutdown, while maintaining network stability through controlled resource management
Solution Approach 2:
The system changes routing parameters dynamically during operation. When devices are hot-swapped or hot-plugged, the bridge device modifies routing table entries, allocating or deallocating routing resources as needed. This parameter change capability enables flexible reconfiguration while maintaining network stability through systematic resource management protocols
Data Source
AI summary
Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt™ transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.