Augmented Multimode Compactor for Test Data Compression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current test response compression techniques in integrated circuits face challenges such as error masking, high hardware overhead, and limited diagnostic capabilities, particularly when dealing with unknown values and multiple errors, which hinder efficient test data reduction and diagnosis.
Innovation Solution
The development of augmented multimode compactors that reduce or avoid the X-masking effect, allowing for unique error signatures and efficient diagnosis, by dividing scan chains into groups and using specific logic gate configurations and output registers to process test response data, enabling flexible trade-offs between compaction ratio, observability, and diagnostic properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional test response compression techniques are used, then test data volume is reduced, but error masking occurs and diagnostic capabilities are limited
Solution Approach 1:
The patent divides scan chains into multiple groups and processes them through separate compression paths with different compactor types (linear feedback shift register, circular path, compactor). This segmentation allows unique error signatures to be generated for different error conditions, preventing error masking while maintaining data compression.
Solution Approach 2:
The patent implements multimode operation where the compactor can switch between different compression modes (full scan compression, partial scan compression, scan chain selective compression) based on test requirements. This dynamic adaptability allows optimization between compression ratio and diagnostic capability for different testing scenarios.
2Measurement precision
If scan chains are divided into groups with specific logic gate configurations, then unique error signatures are achieved, but hardware overhead increases
Solution Approach 1:
The patent designs a universal compactor structure that can perform multiple functions: compression of test responses, generation of unique error signatures, and support for multiple compression modes. The same compactor circuitry serves different purposes depending on the operating mode, reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent changes operational parameters of the compactor (such as feedback tap positions, compression ratio, and mode selection) to achieve different error signature characteristics without changing the fundamental hardware architecture. This allows adaptation to different diagnostic requirements through parameter configuration rather than hardware redesign.
3Productivity
If multiple errors and unknown values are present in test responses, then diagnostic efficiency is enhanced, but error masking effect increases
Solution Approach 1:
The patent converts the potentially harmful effect of multiple errors and unknown values into beneficial diagnostic information by designing the compactor to generate unique error signatures even in the presence of these conditions. The multimode operation allows the system to adapt to different error patterns and maintain diagnostic capability rather than being overwhelmed by error masking.
Solution Approach 2:
The patent incorporates feedback mechanisms in the linear feedback shift register and circular path compactors that continuously monitor and adjust the compression process. This feedback allows the system to detect and compensate for the presence of multiple errors and unknown values, maintaining unique error signatures while enhancing diagnostic efficiency.
Data Source
AI summary
Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. An integrated circuit has circuitry that compacts test response data from scan chains in the integrated circuit under test. In many cases groups of the scan chains are coupled to output registers, such that a same group of scan chains is coupled to sequential elements of different output registers; and the same group is a subset of the scan chains including two or more scan chains. Various computer-implemented methods divide scan chains among at least groups and partitions. The groups disallow sharing a common scan chain from the scan chains, within a particular partition. At least one common scan chain is shared between the groups of different partitions.