Authenticated Memory Encryption Engine Counter Segmentation

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Solution Overview

Problem

Existing technologies face challenges in correctly performing parallel processing of authentication processes using an authentication tree, particularly when access to data assigned to one leaf node conflicts with access to data assigned to another leaf node sharing a common ancestor node.

Innovation Solution

An information processing device equipped with an authenticated memory encryption engine that temporarily stores counters, identifiers, and tags in an authentication tree cache and a data cache. The engine performs cryptographic and authentication processes using an authentication tree for data exchanged between the caches and memory, and delays the update of major counters until minor counters are updated, allowing for parallel processing without conflicts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel access to data assigned to different leaf nodes is performed, then processing performance is improved, but conflicts occur when updating common ancestor nodes

Engineering Contradiction:
Improveprocessing performanceVSAvoidcorrectness of parallel processing
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The counter update process is segmented into two distinct phases: a first phase that updates minor counters (lower-order bits) and a second phase that updates major counters (higher-order bits). This segmentation allows parallel access to different leaf nodes to proceed simultaneously in the first phase without conflict, while the second phase handles major counter updates in a controlled manner, thereby resolving the conflict between parallel processing performance and correctness.

Inventive Principle:
Principle #1Segmentation

2Reliability

If sequential access to data assigned to different leaf nodes is performed, then conflicts during update are avoided, but processing performance deteriorates

Engineering Contradiction:
Improvecorrectness of parallel processingVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The counter update process is segmented into two distinct phases: a first phase that updates minor counters (lower-order bits) and a second phase that updates major counters (higher-order bits). This segmentation allows parallel access to different leaf nodes to proceed simultaneously in the first phase without conflict, while the second phase handles major counter updates in a controlled manner, thereby resolving the conflict between parallel processing performance and correctness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The update process alternates between two periodic phases: Phase 1 updates minor counters and Phase 2 updates major counters. This periodic alternation allows multiple parallel access operations to be processed during Phase 1, and then a single update operation to be processed during Phase 2, effectively batching operations to improve overall throughput while maintaining correctness.

Inventive Principle:
Principle #19Periodic action

3Reliability

If lock mechanism is used to prevent conflicts during parallel access, then data confidentiality is improved, but processing speed decreases due to waiting time

Engineering Contradiction:
Improvedata confidentialityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The counter update process is segmented into two distinct phases: a first phase that updates minor counters (lower-order bits) and a second phase that updates major counters (higher-order bits). This segmentation allows parallel access to different leaf nodes to proceed simultaneously in the first phase without conflict, while the second phase handles major counter updates in a controlled manner, thereby resolving the conflict between parallel processing performance and correctness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The update process alternates between two periodic phases: Phase 1 updates minor counters and Phase 2 updates major counters. This periodic alternation allows multiple parallel access operations to be processed during Phase 1, and then a single update operation to be processed during Phase 2, effectively batching operations to improve overall throughput while maintaining correctness.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250124141A1Information processing device, method for controlling information processing device, and non-transitory computer readable medium
Publication Date: 2025.04.17 NEC CORP
  • US20250124141A1 patent drawing
  • US20250124141A1 patent drawing
  • US20250124141A1 patent drawing

AI summary

An information processing device includes an authenticated memory encryption engine configured to perform a cryptographic process and an authentication process using an authentication tree for data to be exchanged between a data cache and a memory, and perform an authentication process for at least one tag respectively generated in at least one node present on a path from a leaf node to which the data is assigned to a root node, in which a counter assigned to each node in the authentication tree is formed of a major counter and a minor counter, the major counter is shared by a plurality of nodes having a common parent node, and the authenticated memory encryption engine is further configured to be able to wait for a process for updating a value of the major counter which occurs as a result of a process for updating a value of the minor counter.