Authentication Branch Instructions with Deferred Commit Verification
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Solution Overview
Problem
Malicious programmers exploit return-oriented programming (ROP) and jump-oriented programming (JOP) attacks by modifying return addresses in the stack to alter control flow, bypassing Data Execution Prevention techniques, posing a security risk to computing devices.
Innovation Solution
A processor implements a decode unit that identifies indirect control transfer instructions for subroutines, generates cryptographic signatures for return addresses using secure keys, and authenticates these signatures before allowing instruction commitment, ensuring secure handling of subroutine epilogues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic signature authentication is implemented for return addresses, then security against ROP and JOP attacks is improved, but processing time and complexity increase
Solution Approach 1:
The system pre-generates cryptographic signatures for return addresses during the subroutine call and stores them in a cache structure before the actual return instruction executes. When the return instruction is encountered, the pre-computed signature is quickly retrieved and verified instead of performing full cryptographic computation at return time, thus maintaining security while reducing processing time.
Solution Approach 2:
The patent creates a cached copy of the return address signature during the call phase and stores it in a dedicated cache structure. This cached signature is then used for rapid verification during the return phase, eliminating the need to re-compute the cryptographic signature and significantly reducing the time penalty associated with authentication.
2Reliability
If return address authentication is performed before instruction commitment, then control flow security is improved, but instruction processing speed deteriorates
Solution Approach 1:
The cryptographic signature for the return address is computed and cached during the subroutine call execution, before the return instruction is encountered. This preliminary computation allows the return instruction to proceed with rapid signature verification rather than full cryptographic computation, maintaining security while improving processing speed.
Solution Approach 2:
The patent introduces a cache structure as an intermediary between the return address storage and the authentication logic. This cache holds pre-computed signatures and enables fast verification by the authentication unit, decoupling the security verification process from the critical instruction processing path and minimizing impact on overall execution speed.
3Reliability
If cryptographic signatures are generated and verified for each return address, then protection against malicious code execution is improved, but device complexity increases
Solution Approach 1:
The authentication system is divided into separate functional modules: a signature generation unit that operates during subroutine calls, a cache structure for storing pre-computed signatures, and a verification unit that operates during return instructions. This segmentation allows each component to be optimized independently and integrated into the existing processor architecture with minimal disruption.
Solution Approach 2:
The patent uses a cache structure to store copies of pre-computed return address signatures. This caching mechanism eliminates the need for complex real-time cryptographic computation during return instructions, simplifying the verification process while maintaining strong security protection against malicious code execution.
Data Source
AI summary
Systems, apparatuses, and methods for efficient handling of subroutine epilogues. When an indirect control transfer instruction corresponding to a procedure return for a subroutine is identified, the return address and a signature are retrieved from one or more of a return address stack and the memory stack. An authenticator generates a signature based on at least a portion of the retrieved return address. While the signature is being generated, instruction processing speculatively continues. No instructions are permitted to commit yet. The generated signature is later compared to a copy of the signature generated earlier during the corresponding procedure call. A mismatch causes an exception.