Authentication Memory Pairing Against Power Outage Counter Attacks
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Solution Overview
Problem
Existing authentication processes in electronic devices are vulnerable to power outage attacks, which can compromise the integrity of failure counters used to prevent unauthorized access.
Innovation Solution
A protection method involving a non-volatile memory system with paired memory cells that rewrite data based on authentication success or failure, incrementing a failure counter, and switching active pairs to secure counter increments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a failure counter is used to track authentication attempts, then security against brute force attacks is improved, but the counter becomes vulnerable to power outage attacks that can reset or corrupt the counter value
Solution Approach 1:
The memory system is segmented into multiple pairs of memory cells instead of using a single counter location. Each pair consists of a first memory cell and a second memory cell, allowing the system to distribute counter state information across multiple physical locations, thereby protecting against power outage attacks that might corrupt a single location.
Solution Approach 2:
Different memory cells within each pair serve different functional purposes: the first memory cell stores the counter value while the second memory cell stores verification data. This local differentiation allows the system to verify counter integrity by comparing data across cells, protecting against power outage corruption.
2Reliability
If authentication process integrity is protected through multiple memory cells and verification steps, then security against power outage attacks is improved, but device complexity increases
Solution Approach 1:
The memory structure is divided into multiple pairs of cells, where each pair handles a portion of the counter state. This segmentation allows verification to be performed on individual pairs rather than requiring complex system-wide verification, managing complexity through modular organization.
Solution Approach 2:
The system performs preliminary verification by checking the second memory cell data against expected values before accepting counter updates. This preliminary action prevents corrupted data from propagating through the system, maintaining integrity without requiring complex real-time monitoring.
3Measurement precision
If the second memory cell is rewritten with verification data and a new pair is activated after each failure, then detection of power outage attacks is improved, but the number of memory operations increases
Solution Approach 1:
The system performs verification operations periodically at key points in the authentication process (after counter increment, before acceptance of new counter value). This periodic verification provides adequate security without requiring continuous monitoring that would significantly impact processing speed.
Solution Approach 2:
Verification data is prepared and stored in the second memory cell in advance, before the actual counter update occurs. This preliminary action allows rapid verification during the authentication process without requiring complex real-time computations, maintaining processing efficiency.
Data Source
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AI summary
This description relates to a method for protecting (200) an authentication method (201) of an electronic device comprising a memory (102) consisting of a set (E) of pairs ((ok(1), nok(1)), ..., (ok(N), nok(N)) of memory cells, of which at least one first pair ((ok(1), nok(1)) comprises a first memory cell (ok(1)) storing a first piece of data (Init) and a second memory cell (nok(1)) storing a second piece of data (Init), the first pair being designated as the active pair in which: - upon each success of the authentication method (201), the first memory cell is rewritten with a third piece of data (Random); - upon each failure of the authentication method, the second memory cell is rewritten with a fourth piece of data (Random), then a failure counter is incremented and fifth pieces of data (Init) are written to a second pair ((ok(2), nok(2))) of cells memory, the second couple becoming the active couple.